dt-bindings: Changes for v5.6-rc1
This contains a conversion of the Tegra124 EMC bindings to json-schema as well as the addition of the bindings for the memory subsystem found on Tegra186 and Tegra194. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4ZDFwTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoQf4EACrBQLZaB/icm92vqFk4zt39sdmxTat 7SmBbhe5LdXplMIV5xZY07DscRgl7RHfcxX1Sl6IOo78oKodEhM6USd8juwobq+E GcOVgZ3v+fLTiFIOQcOI3Sa96jq/E+sPzQzgD45foF79xlSox79s5dE4xXjCKG8b mN5zEpZYaIkbOxsLqdKSb4p45XUIVB9YYhRPNNds5j7gEg0UgufnrRLp/r1QPDzS RjMCngFEAs9bat8N2JUJJS9xvQM8KamW/HIwkpBQLujkBfuO+QHqpNrRhe5h2hOn Ui3Y5Lbn4eCvac0nfr9APK0j++BkRKW+2i+2R0YTx8ZqqpDwl4ox4cJDKwtk46Xh KcBkvcvwAQE4NjnEUDBwRRlW446SqfVpnRhTM5y+MHhSG/SyLx4PMydahhsdUNpk eeCVOyiEOQufwBHd4waR+M0tHUqgc1gQ5xdKZ6f5vKhQEGlMcu0L9jlgDNZaOg7L LWFqqzNnRdmdS4plctv67DqbjXBUZ73wxgs2OjUofP+MGUVT2jUjLbW7XmAfl903 5LwXx8mMZIjEnYo84IyylYDC/u8FGT3T4RnFWNuWrjHCz7+qVv+2v3CF6fBFrL// KcZY5m/Kb04dSmQCvW2/2D3LnLGDgg8p3vzUgmBw1VRpfPVvvhY1JFdVBcw9S0iI 6poWBdVfrMEsag== =iPZ2 -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.6-rc1 This contains a conversion of the Tegra124 EMC bindings to json-schema as well as the addition of the bindings for the memory subsystem found on Tegra186 and Tegra194. * tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra186 memory subsystem dt-bindings: memory: Add Tegra194 memory controller header dt-bindings: memory: Add Tegra186 memory client IDs dt-bindings: memory-controller: Convert Tegra124 EMC to json-schema Link: https://lore.kernel.org/r/20200111003553.2411874-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
e64d0098dd
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@ -1,374 +0,0 @@
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NVIDIA Tegra124 SoC EMC (external memory controller)
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====================================================
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Required properties :
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- compatible : Should be "nvidia,tegra124-emc".
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- reg : physical base address and length of the controller's registers.
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- nvidia,memory-controller : phandle of the MC driver.
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The node should contain a "emc-timings" subnode for each supported RAM type
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(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
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being its RAM_CODE.
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
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used for.
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Each "emc-timings" node should contain a "timing" subnode for every supported
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EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
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their unit address.
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Required properties for "timing" nodes :
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- clock-frequency : Should contain the memory clock rate in Hz.
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- The following properties contain EMC timing characterization values
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(specified in the board documentation) :
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- nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
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- nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
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- nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
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- nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
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- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
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- nvidia,emc-cfg : EMC_CFG
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- nvidia,emc-cfg-2 : EMC_CFG_2
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- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
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- nvidia,emc-mode-1 : Mode Register 1
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- nvidia,emc-mode-2 : Mode Register 2
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- nvidia,emc-mode-4 : Mode Register 4
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- nvidia,emc-mode-reset : Mode Register 0
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- nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
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- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
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- nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
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- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
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- nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
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- nvidia,emc-configuration : EMC timing characterization data. These are the
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registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
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be specified, according to the board documentation:
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EMC_RC
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EMC_RFC
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EMC_RFC_SLR
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EMC_RAS
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EMC_RP
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EMC_R2W
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EMC_W2R
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EMC_R2P
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EMC_W2P
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EMC_RD_RCD
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EMC_WR_RCD
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EMC_RRD
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EMC_REXT
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EMC_WEXT
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EMC_WDV
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EMC_WDV_MASK
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EMC_QUSE
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EMC_QUSE_WIDTH
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EMC_IBDLY
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EMC_EINPUT
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EMC_EINPUT_DURATION
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EMC_PUTERM_EXTRA
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EMC_PUTERM_WIDTH
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EMC_PUTERM_ADJ
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EMC_CDB_CNTL_1
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EMC_CDB_CNTL_2
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EMC_CDB_CNTL_3
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EMC_QRST
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EMC_QSAFE
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EMC_RDV
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EMC_RDV_MASK
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EMC_REFRESH
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EMC_BURST_REFRESH_NUM
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EMC_PRE_REFRESH_REQ_CNT
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EMC_PDEX2WR
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EMC_PDEX2RD
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EMC_PCHG2PDEN
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EMC_ACT2PDEN
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EMC_AR2PDEN
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EMC_RW2PDEN
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EMC_TXSR
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EMC_TXSRDLL
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EMC_TCKE
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EMC_TCKESR
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EMC_TPD
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EMC_TFAW
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EMC_TRPAB
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EMC_TCLKSTABLE
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EMC_TCLKSTOP
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EMC_TREFBW
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EMC_FBIO_CFG6
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EMC_ODT_WRITE
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EMC_ODT_READ
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EMC_FBIO_CFG5
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EMC_CFG_DIG_DLL
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EMC_CFG_DIG_DLL_PERIOD
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EMC_DLL_XFORM_DQS0
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EMC_DLL_XFORM_DQS1
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EMC_DLL_XFORM_DQS2
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EMC_DLL_XFORM_DQS3
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EMC_DLL_XFORM_DQS4
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EMC_DLL_XFORM_DQS5
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EMC_DLL_XFORM_DQS6
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EMC_DLL_XFORM_DQS7
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EMC_DLL_XFORM_DQS8
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EMC_DLL_XFORM_DQS9
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EMC_DLL_XFORM_DQS10
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EMC_DLL_XFORM_DQS11
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EMC_DLL_XFORM_DQS12
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EMC_DLL_XFORM_DQS13
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EMC_DLL_XFORM_DQS14
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EMC_DLL_XFORM_DQS15
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EMC_DLL_XFORM_QUSE0
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EMC_DLL_XFORM_QUSE1
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EMC_DLL_XFORM_QUSE2
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EMC_DLL_XFORM_QUSE3
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EMC_DLL_XFORM_QUSE4
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EMC_DLL_XFORM_QUSE5
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EMC_DLL_XFORM_QUSE6
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EMC_DLL_XFORM_QUSE7
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EMC_DLL_XFORM_ADDR0
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EMC_DLL_XFORM_ADDR1
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EMC_DLL_XFORM_ADDR2
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EMC_DLL_XFORM_ADDR3
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EMC_DLL_XFORM_ADDR4
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EMC_DLL_XFORM_ADDR5
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EMC_DLL_XFORM_QUSE8
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EMC_DLL_XFORM_QUSE9
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EMC_DLL_XFORM_QUSE10
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EMC_DLL_XFORM_QUSE11
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EMC_DLL_XFORM_QUSE12
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EMC_DLL_XFORM_QUSE13
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EMC_DLL_XFORM_QUSE14
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EMC_DLL_XFORM_QUSE15
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EMC_DLI_TRIM_TXDQS0
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EMC_DLI_TRIM_TXDQS1
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EMC_DLI_TRIM_TXDQS2
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EMC_DLI_TRIM_TXDQS3
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EMC_DLI_TRIM_TXDQS4
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EMC_DLI_TRIM_TXDQS5
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EMC_DLI_TRIM_TXDQS6
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EMC_DLI_TRIM_TXDQS7
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EMC_DLI_TRIM_TXDQS8
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EMC_DLI_TRIM_TXDQS9
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EMC_DLI_TRIM_TXDQS10
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EMC_DLI_TRIM_TXDQS11
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EMC_DLI_TRIM_TXDQS12
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EMC_DLI_TRIM_TXDQS13
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EMC_DLI_TRIM_TXDQS14
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EMC_DLI_TRIM_TXDQS15
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EMC_DLL_XFORM_DQ0
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EMC_DLL_XFORM_DQ1
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EMC_DLL_XFORM_DQ2
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EMC_DLL_XFORM_DQ3
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EMC_DLL_XFORM_DQ4
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EMC_DLL_XFORM_DQ5
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EMC_DLL_XFORM_DQ6
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EMC_DLL_XFORM_DQ7
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EMC_XM2CMDPADCTRL
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EMC_XM2CMDPADCTRL4
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EMC_XM2CMDPADCTRL5
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EMC_XM2DQPADCTRL2
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EMC_XM2DQPADCTRL3
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EMC_XM2CLKPADCTRL
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EMC_XM2CLKPADCTRL2
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EMC_XM2COMPPADCTRL
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EMC_XM2VTTGENPADCTRL
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EMC_XM2VTTGENPADCTRL2
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EMC_XM2VTTGENPADCTRL3
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EMC_XM2DQSPADCTRL3
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EMC_XM2DQSPADCTRL4
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EMC_XM2DQSPADCTRL5
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EMC_XM2DQSPADCTRL6
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EMC_DSR_VTTGEN_DRV
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EMC_TXDSRVTTGEN
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EMC_FBIO_SPARE
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EMC_ZCAL_WAIT_CNT
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EMC_MRS_WAIT_CNT2
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EMC_CTT
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EMC_CTT_DURATION
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EMC_CFG_PIPE
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EMC_DYN_SELF_REF_CONTROL
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EMC_QPOP
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Example SoC include file:
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/ {
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emc@7001b000 {
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compatible = "nvidia,tegra124-emc";
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reg = <0x0 0x7001b000 0x0 0x1000>;
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nvidia,memory-controller = <&mc>;
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};
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};
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Example board file:
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/ {
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emc@7001b000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emc-zcal-cnt-long = <0x00000042>;
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nvidia,emc-auto-cal-interval = <0x001fffff>;
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nvidia,emc-ctt-term-ctrl = <0x00000802>;
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nvidia,emc-cfg = <0x73240000>;
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nvidia,emc-cfg-2 = <0x000008c5>;
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nvidia,emc-sel-dpd-ctrl = <0x00040128>;
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nvidia,emc-bgbias-ctl0 = <0x00000008>;
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nvidia,emc-auto-cal-config = <0xa1430000>;
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nvidia,emc-auto-cal-config2 = <0x00000000>;
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nvidia,emc-auto-cal-config3 = <0x00000000>;
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nvidia,emc-mode-reset = <0x80001221>;
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nvidia,emc-mode-1 = <0x80100003>;
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nvidia,emc-mode-2 = <0x80200008>;
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nvidia,emc-mode-4 = <0x00000000>;
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nvidia,emc-configuration = <
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0x00000000 /* EMC_RC */
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0x00000003 /* EMC_RFC */
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0x00000000 /* EMC_RFC_SLR */
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0x00000000 /* EMC_RAS */
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0x00000000 /* EMC_RP */
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0x00000004 /* EMC_R2W */
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0x0000000a /* EMC_W2R */
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0x00000003 /* EMC_R2P */
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0x0000000b /* EMC_W2P */
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0x00000000 /* EMC_RD_RCD */
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0x00000000 /* EMC_WR_RCD */
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0x00000003 /* EMC_RRD */
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0x00000003 /* EMC_REXT */
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0x00000000 /* EMC_WEXT */
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0x00000006 /* EMC_WDV */
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0x00000006 /* EMC_WDV_MASK */
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0x00000006 /* EMC_QUSE */
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0x00000002 /* EMC_QUSE_WIDTH */
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0x00000000 /* EMC_IBDLY */
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0x00000005 /* EMC_EINPUT */
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0x00000005 /* EMC_EINPUT_DURATION */
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0x00010000 /* EMC_PUTERM_EXTRA */
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0x00000003 /* EMC_PUTERM_WIDTH */
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0x00000000 /* EMC_PUTERM_ADJ */
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0x00000000 /* EMC_CDB_CNTL_1 */
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0x00000000 /* EMC_CDB_CNTL_2 */
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0x00000000 /* EMC_CDB_CNTL_3 */
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0x00000004 /* EMC_QRST */
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0x0000000c /* EMC_QSAFE */
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0x0000000d /* EMC_RDV */
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0x0000000f /* EMC_RDV_MASK */
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0x00000060 /* EMC_REFRESH */
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0x00000000 /* EMC_BURST_REFRESH_NUM */
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0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
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0x00000002 /* EMC_PDEX2WR */
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0x00000002 /* EMC_PDEX2RD */
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0x00000001 /* EMC_PCHG2PDEN */
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0x00000000 /* EMC_ACT2PDEN */
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0x00000007 /* EMC_AR2PDEN */
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0x0000000f /* EMC_RW2PDEN */
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0x00000005 /* EMC_TXSR */
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0x00000005 /* EMC_TXSRDLL */
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0x00000004 /* EMC_TCKE */
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0x00000005 /* EMC_TCKESR */
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0x00000004 /* EMC_TPD */
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0x00000000 /* EMC_TFAW */
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0x00000000 /* EMC_TRPAB */
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0x00000005 /* EMC_TCLKSTABLE */
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0x00000005 /* EMC_TCLKSTOP */
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0x00000064 /* EMC_TREFBW */
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0x00000000 /* EMC_FBIO_CFG6 */
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0x00000000 /* EMC_ODT_WRITE */
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0x00000000 /* EMC_ODT_READ */
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0x106aa298 /* EMC_FBIO_CFG5 */
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0x002c00a0 /* EMC_CFG_DIG_DLL */
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0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
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0x00064000 /* EMC_DLL_XFORM_DQS0 */
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0x00064000 /* EMC_DLL_XFORM_DQS1 */
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0x00064000 /* EMC_DLL_XFORM_DQS2 */
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0x00064000 /* EMC_DLL_XFORM_DQS3 */
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0x00064000 /* EMC_DLL_XFORM_DQS4 */
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0x00064000 /* EMC_DLL_XFORM_DQS5 */
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0x00064000 /* EMC_DLL_XFORM_DQS6 */
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0x00064000 /* EMC_DLL_XFORM_DQS7 */
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0x00064000 /* EMC_DLL_XFORM_DQS8 */
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0x00064000 /* EMC_DLL_XFORM_DQS9 */
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0x00064000 /* EMC_DLL_XFORM_DQS10 */
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0x00064000 /* EMC_DLL_XFORM_DQS11 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS12 */
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||||
0x00064000 /* EMC_DLL_XFORM_DQS13 */
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0x00064000 /* EMC_DLL_XFORM_DQS14 */
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0x00064000 /* EMC_DLL_XFORM_DQS15 */
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0x00000000 /* EMC_DLL_XFORM_QUSE0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
|
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0x00000000 /* EMC_DLL_XFORM_ADDR0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
|
||||
0x10000280 /* EMC_XM2CMDPADCTRL */
|
||||
0x00000000 /* EMC_XM2CMDPADCTRL4 */
|
||||
0x00111111 /* EMC_XM2CMDPADCTRL5 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL2 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL3 */
|
||||
0x77ffc081 /* EMC_XM2CLKPADCTRL */
|
||||
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
|
||||
0x81f1f108 /* EMC_XM2COMPPADCTRL */
|
||||
0x07070004 /* EMC_XM2VTTGENPADCTRL */
|
||||
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
|
||||
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL3 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL4 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL5 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL6 */
|
||||
0x0000003f /* EMC_DSR_VTTGEN_DRV */
|
||||
0x00000007 /* EMC_TXDSRVTTGEN */
|
||||
0x00000000 /* EMC_FBIO_SPARE */
|
||||
0x00000042 /* EMC_ZCAL_WAIT_CNT */
|
||||
0x000e000e /* EMC_MRS_WAIT_CNT2 */
|
||||
0x00000000 /* EMC_CTT */
|
||||
0x00000003 /* EMC_CTT_DURATION */
|
||||
0x0000f2f3 /* EMC_CFG_PIPE */
|
||||
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
|
||||
0x0000000a /* EMC_QPOP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,528 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra124 SoC External Memory Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The EMC interfaces with the off-chip SDRAM to service the request stream
|
||||
sent from the memory controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra124-emc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: external memory clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: emc
|
||||
|
||||
nvidia,memory-controller:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the memory controller node
|
||||
|
||||
patternProperties:
|
||||
"^emc-timings-[0-9]+$":
|
||||
type: object
|
||||
properties:
|
||||
nvidia,ram-code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
|
||||
this timing set is used for
|
||||
|
||||
patternProperties:
|
||||
"^timing-[0-9]+$":
|
||||
type: object
|
||||
properties:
|
||||
clock-frequency:
|
||||
description:
|
||||
external memory clock rate in Hz
|
||||
minimum: 1000000
|
||||
maximum: 1000000000
|
||||
|
||||
nvidia,emc-auto-cal-config:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_AUTO_CAL_CONFIG register for this set of
|
||||
timings
|
||||
|
||||
nvidia,emc-auto-cal-config2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_AUTO_CAL_CONFIG2 register for this set of
|
||||
timings
|
||||
|
||||
nvidia,emc-auto-cal-config3:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_AUTO_CAL_CONFIG3 register for this set of
|
||||
timings
|
||||
|
||||
nvidia,emc-auto-cal-interval:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
pad calibration interval in microseconds
|
||||
minimum: 0
|
||||
maximum: 2097151
|
||||
|
||||
nvidia,emc-bgbias-ctl0:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_BGBIAS_CTL0 register for this set of timings
|
||||
|
||||
nvidia,emc-cfg:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_CFG register for this set of timings
|
||||
|
||||
nvidia,emc-cfg-2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_CFG_2 register for this set of timings
|
||||
|
||||
nvidia,emc-ctt-term-ctrl:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_CTT_TERM_CTRL register for this set of timings
|
||||
|
||||
nvidia,emc-mode-1:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_MRW register for this set of timings
|
||||
|
||||
nvidia,emc-mode-2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_MRW2 register for this set of timings
|
||||
|
||||
nvidia,emc-mode-4:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_MRW4 register for this set of timings
|
||||
|
||||
nvidia,emc-mode-reset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
reset value of the EMC_MRS register for this set of timings
|
||||
|
||||
nvidia,emc-mrs-wait-cnt:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMR_MRS_WAIT_CNT register for this set of timings
|
||||
|
||||
nvidia,emc-sel-dpd-ctrl:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_SEL_DPD_CTRL register for this set of timings
|
||||
|
||||
nvidia,emc-xm2dqspadctrl2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_XM2DQSPADCTRL2 register for this set of timings
|
||||
|
||||
nvidia,emc-zcal-cnt-long:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
number of EMC clocks to wait before issuing any commands after
|
||||
clock change
|
||||
minimum: 0
|
||||
maximum: 1023
|
||||
|
||||
nvidia,emc-zcal-interval:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
value of the EMC_ZCAL_INTERVAL register for this set of timings
|
||||
|
||||
nvidia,emc-configuration:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
EMC timing characterization data. These are the registers (see
|
||||
section "15.6.2 EMC Registers" in the TRM) whose values need to
|
||||
be specified, according to the board documentation.
|
||||
items:
|
||||
- description: EMC_RC
|
||||
- description: EMC_RFC
|
||||
- description: EMC_RFC_SLR
|
||||
- description: EMC_RAS
|
||||
- description: EMC_RP
|
||||
- description: EMC_R2W
|
||||
- description: EMC_W2R
|
||||
- description: EMC_R2P
|
||||
- description: EMC_W2P
|
||||
- description: EMC_RD_RCD
|
||||
- description: EMC_WR_RCD
|
||||
- description: EMC_RRD
|
||||
- description: EMC_REXT
|
||||
- description: EMC_WEXT
|
||||
- description: EMC_WDV
|
||||
- description: EMC_WDV_MASK
|
||||
- description: EMC_QUSE
|
||||
- description: EMC_QUSE_WIDTH
|
||||
- description: EMC_IBDLY
|
||||
- description: EMC_EINPUT
|
||||
- description: EMC_EINPUT_DURATION
|
||||
- description: EMC_PUTERM_EXTRA
|
||||
- description: EMC_PUTERM_WIDTH
|
||||
- description: EMC_PUTERM_ADJ
|
||||
- description: EMC_CDB_CNTL_1
|
||||
- description: EMC_CDB_CNTL_2
|
||||
- description: EMC_CDB_CNTL_3
|
||||
- description: EMC_QRST
|
||||
- description: EMC_QSAFE
|
||||
- description: EMC_RDV
|
||||
- description: EMC_RDV_MASK
|
||||
- description: EMC_REFRESH
|
||||
- description: EMC_BURST_REFRESH_NUM
|
||||
- description: EMC_PRE_REFRESH_REQ_CNT
|
||||
- description: EMC_PDEX2WR
|
||||
- description: EMC_PDEX2RD
|
||||
- description: EMC_PCHG2PDEN
|
||||
- description: EMC_ACT2PDEN
|
||||
- description: EMC_AR2PDEN
|
||||
- description: EMC_RW2PDEN
|
||||
- description: EMC_TXSR
|
||||
- description: EMC_TXSRDLL
|
||||
- description: EMC_TCKE
|
||||
- description: EMC_TCKESR
|
||||
- description: EMC_TPD
|
||||
- description: EMC_TFAW
|
||||
- description: EMC_TRPAB
|
||||
- description: EMC_TCLKSTABLE
|
||||
- description: EMC_TCLKSTOP
|
||||
- description: EMC_TREFBW
|
||||
- description: EMC_FBIO_CFG6
|
||||
- description: EMC_ODT_WRITE
|
||||
- description: EMC_ODT_READ
|
||||
- description: EMC_FBIO_CFG5
|
||||
- description: EMC_CFG_DIG_DLL
|
||||
- description: EMC_CFG_DIG_DLL_PERIOD
|
||||
- description: EMC_DLL_XFORM_DQS0
|
||||
- description: EMC_DLL_XFORM_DQS1
|
||||
- description: EMC_DLL_XFORM_DQS2
|
||||
- description: EMC_DLL_XFORM_DQS3
|
||||
- description: EMC_DLL_XFORM_DQS4
|
||||
- description: EMC_DLL_XFORM_DQS5
|
||||
- description: EMC_DLL_XFORM_DQS6
|
||||
- description: EMC_DLL_XFORM_DQS7
|
||||
- description: EMC_DLL_XFORM_DQS8
|
||||
- description: EMC_DLL_XFORM_DQS9
|
||||
- description: EMC_DLL_XFORM_DQS10
|
||||
- description: EMC_DLL_XFORM_DQS11
|
||||
- description: EMC_DLL_XFORM_DQS12
|
||||
- description: EMC_DLL_XFORM_DQS13
|
||||
- description: EMC_DLL_XFORM_DQS14
|
||||
- description: EMC_DLL_XFORM_DQS15
|
||||
- description: EMC_DLL_XFORM_QUSE0
|
||||
- description: EMC_DLL_XFORM_QUSE1
|
||||
- description: EMC_DLL_XFORM_QUSE2
|
||||
- description: EMC_DLL_XFORM_QUSE3
|
||||
- description: EMC_DLL_XFORM_QUSE4
|
||||
- description: EMC_DLL_XFORM_QUSE5
|
||||
- description: EMC_DLL_XFORM_QUSE6
|
||||
- description: EMC_DLL_XFORM_QUSE7
|
||||
- description: EMC_DLL_XFORM_ADDR0
|
||||
- description: EMC_DLL_XFORM_ADDR1
|
||||
- description: EMC_DLL_XFORM_ADDR2
|
||||
- description: EMC_DLL_XFORM_ADDR3
|
||||
- description: EMC_DLL_XFORM_ADDR4
|
||||
- description: EMC_DLL_XFORM_ADDR5
|
||||
- description: EMC_DLL_XFORM_QUSE8
|
||||
- description: EMC_DLL_XFORM_QUSE9
|
||||
- description: EMC_DLL_XFORM_QUSE10
|
||||
- description: EMC_DLL_XFORM_QUSE11
|
||||
- description: EMC_DLL_XFORM_QUSE12
|
||||
- description: EMC_DLL_XFORM_QUSE13
|
||||
- description: EMC_DLL_XFORM_QUSE14
|
||||
- description: EMC_DLL_XFORM_QUSE15
|
||||
- description: EMC_DLI_TRIM_TXDQS0
|
||||
- description: EMC_DLI_TRIM_TXDQS1
|
||||
- description: EMC_DLI_TRIM_TXDQS2
|
||||
- description: EMC_DLI_TRIM_TXDQS3
|
||||
- description: EMC_DLI_TRIM_TXDQS4
|
||||
- description: EMC_DLI_TRIM_TXDQS5
|
||||
- description: EMC_DLI_TRIM_TXDQS6
|
||||
- description: EMC_DLI_TRIM_TXDQS7
|
||||
- description: EMC_DLI_TRIM_TXDQS8
|
||||
- description: EMC_DLI_TRIM_TXDQS9
|
||||
- description: EMC_DLI_TRIM_TXDQS10
|
||||
- description: EMC_DLI_TRIM_TXDQS11
|
||||
- description: EMC_DLI_TRIM_TXDQS12
|
||||
- description: EMC_DLI_TRIM_TXDQS13
|
||||
- description: EMC_DLI_TRIM_TXDQS14
|
||||
- description: EMC_DLI_TRIM_TXDQS15
|
||||
- description: EMC_DLL_XFORM_DQ0
|
||||
- description: EMC_DLL_XFORM_DQ1
|
||||
- description: EMC_DLL_XFORM_DQ2
|
||||
- description: EMC_DLL_XFORM_DQ3
|
||||
- description: EMC_DLL_XFORM_DQ4
|
||||
- description: EMC_DLL_XFORM_DQ5
|
||||
- description: EMC_DLL_XFORM_DQ6
|
||||
- description: EMC_DLL_XFORM_DQ7
|
||||
- description: EMC_XM2CMDPADCTRL
|
||||
- description: EMC_XM2CMDPADCTRL4
|
||||
- description: EMC_XM2CMDPADCTRL5
|
||||
- description: EMC_XM2DQPADCTRL2
|
||||
- description: EMC_XM2DQPADCTRL3
|
||||
- description: EMC_XM2CLKPADCTRL
|
||||
- description: EMC_XM2CLKPADCTRL2
|
||||
- description: EMC_XM2COMPPADCTRL
|
||||
- description: EMC_XM2VTTGENPADCTRL
|
||||
- description: EMC_XM2VTTGENPADCTRL2
|
||||
- description: EMC_XM2VTTGENPADCTRL3
|
||||
- description: EMC_XM2DQSPADCTRL3
|
||||
- description: EMC_XM2DQSPADCTRL4
|
||||
- description: EMC_XM2DQSPADCTRL5
|
||||
- description: EMC_XM2DQSPADCTRL6
|
||||
- description: EMC_DSR_VTTGEN_DRV
|
||||
- description: EMC_TXDSRVTTGEN
|
||||
- description: EMC_FBIO_SPARE
|
||||
- description: EMC_ZCAL_WAIT_CNT
|
||||
- description: EMC_MRS_WAIT_CNT2
|
||||
- description: EMC_CTT
|
||||
- description: EMC_CTT_DURATION
|
||||
- description: EMC_CFG_PIPE
|
||||
- description: EMC_DYN_SELF_REF_CONTROL
|
||||
- description: EMC_QPOP
|
||||
|
||||
required:
|
||||
- clock-frequency
|
||||
- nvidia,emc-auto-cal-config
|
||||
- nvidia,emc-auto-cal-config2
|
||||
- nvidia,emc-auto-cal-config3
|
||||
- nvidia,emc-auto-cal-interval
|
||||
- nvidia,emc-bgbias-ctl0
|
||||
- nvidia,emc-cfg
|
||||
- nvidia,emc-cfg-2
|
||||
- nvidia,emc-ctt-term-ctrl
|
||||
- nvidia,emc-mode-1
|
||||
- nvidia,emc-mode-2
|
||||
- nvidia,emc-mode-4
|
||||
- nvidia,emc-mode-reset
|
||||
- nvidia,emc-mrs-wait-cnt
|
||||
- nvidia,emc-sel-dpd-ctrl
|
||||
- nvidia,emc-xm2dqspadctrl2
|
||||
- nvidia,emc-zcal-cnt-long
|
||||
- nvidia,emc-zcal-interval
|
||||
- nvidia,emc-configuration
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- nvidia,memory-controller
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mc: memory-controller@70019000 {
|
||||
compatible = "nvidia,tegra124-mc";
|
||||
reg = <0x0 0x70019000 0x0 0x1000>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_MC>;
|
||||
clock-names = "mc";
|
||||
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
external-memory-controller@7001b000 {
|
||||
compatible = "nvidia,tegra124-emc";
|
||||
reg = <0x0 0x7001b000 0x0 0x1000>;
|
||||
clocks = <&car TEGRA124_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
|
||||
emc-timings-0 {
|
||||
nvidia,ram-code = <3>;
|
||||
|
||||
timing-0 {
|
||||
clock-frequency = <12750000>;
|
||||
|
||||
nvidia,emc-zcal-cnt-long = <0x00000042>;
|
||||
nvidia,emc-auto-cal-interval = <0x001fffff>;
|
||||
nvidia,emc-ctt-term-ctrl = <0x00000802>;
|
||||
nvidia,emc-cfg = <0x73240000>;
|
||||
nvidia,emc-cfg-2 = <0x000008c5>;
|
||||
nvidia,emc-sel-dpd-ctrl = <0x00040128>;
|
||||
nvidia,emc-bgbias-ctl0 = <0x00000008>;
|
||||
nvidia,emc-auto-cal-config = <0xa1430000>;
|
||||
nvidia,emc-auto-cal-config2 = <0x00000000>;
|
||||
nvidia,emc-auto-cal-config3 = <0x00000000>;
|
||||
nvidia,emc-mode-reset = <0x80001221>;
|
||||
nvidia,emc-mode-1 = <0x80100003>;
|
||||
nvidia,emc-mode-2 = <0x80200008>;
|
||||
nvidia,emc-mode-4 = <0x00000000>;
|
||||
|
||||
nvidia,emc-configuration = <
|
||||
0x00000000 /* EMC_RC */
|
||||
0x00000003 /* EMC_RFC */
|
||||
0x00000000 /* EMC_RFC_SLR */
|
||||
0x00000000 /* EMC_RAS */
|
||||
0x00000000 /* EMC_RP */
|
||||
0x00000004 /* EMC_R2W */
|
||||
0x0000000a /* EMC_W2R */
|
||||
0x00000003 /* EMC_R2P */
|
||||
0x0000000b /* EMC_W2P */
|
||||
0x00000000 /* EMC_RD_RCD */
|
||||
0x00000000 /* EMC_WR_RCD */
|
||||
0x00000003 /* EMC_RRD */
|
||||
0x00000003 /* EMC_REXT */
|
||||
0x00000000 /* EMC_WEXT */
|
||||
0x00000006 /* EMC_WDV */
|
||||
0x00000006 /* EMC_WDV_MASK */
|
||||
0x00000006 /* EMC_QUSE */
|
||||
0x00000002 /* EMC_QUSE_WIDTH */
|
||||
0x00000000 /* EMC_IBDLY */
|
||||
0x00000005 /* EMC_EINPUT */
|
||||
0x00000005 /* EMC_EINPUT_DURATION */
|
||||
0x00010000 /* EMC_PUTERM_EXTRA */
|
||||
0x00000003 /* EMC_PUTERM_WIDTH */
|
||||
0x00000000 /* EMC_PUTERM_ADJ */
|
||||
0x00000000 /* EMC_CDB_CNTL_1 */
|
||||
0x00000000 /* EMC_CDB_CNTL_2 */
|
||||
0x00000000 /* EMC_CDB_CNTL_3 */
|
||||
0x00000004 /* EMC_QRST */
|
||||
0x0000000c /* EMC_QSAFE */
|
||||
0x0000000d /* EMC_RDV */
|
||||
0x0000000f /* EMC_RDV_MASK */
|
||||
0x00000060 /* EMC_REFRESH */
|
||||
0x00000000 /* EMC_BURST_REFRESH_NUM */
|
||||
0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
|
||||
0x00000002 /* EMC_PDEX2WR */
|
||||
0x00000002 /* EMC_PDEX2RD */
|
||||
0x00000001 /* EMC_PCHG2PDEN */
|
||||
0x00000000 /* EMC_ACT2PDEN */
|
||||
0x00000007 /* EMC_AR2PDEN */
|
||||
0x0000000f /* EMC_RW2PDEN */
|
||||
0x00000005 /* EMC_TXSR */
|
||||
0x00000005 /* EMC_TXSRDLL */
|
||||
0x00000004 /* EMC_TCKE */
|
||||
0x00000005 /* EMC_TCKESR */
|
||||
0x00000004 /* EMC_TPD */
|
||||
0x00000000 /* EMC_TFAW */
|
||||
0x00000000 /* EMC_TRPAB */
|
||||
0x00000005 /* EMC_TCLKSTABLE */
|
||||
0x00000005 /* EMC_TCLKSTOP */
|
||||
0x00000064 /* EMC_TREFBW */
|
||||
0x00000000 /* EMC_FBIO_CFG6 */
|
||||
0x00000000 /* EMC_ODT_WRITE */
|
||||
0x00000000 /* EMC_ODT_READ */
|
||||
0x106aa298 /* EMC_FBIO_CFG5 */
|
||||
0x002c00a0 /* EMC_CFG_DIG_DLL */
|
||||
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS0 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS1 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS2 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS3 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS4 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS5 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS6 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS7 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS8 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS9 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS10 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS11 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS12 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS13 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS14 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS15 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
|
||||
0x10000280 /* EMC_XM2CMDPADCTRL */
|
||||
0x00000000 /* EMC_XM2CMDPADCTRL4 */
|
||||
0x00111111 /* EMC_XM2CMDPADCTRL5 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL2 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL3 */
|
||||
0x77ffc081 /* EMC_XM2CLKPADCTRL */
|
||||
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
|
||||
0x81f1f108 /* EMC_XM2COMPPADCTRL */
|
||||
0x07070004 /* EMC_XM2VTTGENPADCTRL */
|
||||
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
|
||||
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL3 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL4 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL5 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL6 */
|
||||
0x0000003f /* EMC_DSR_VTTGEN_DRV */
|
||||
0x00000007 /* EMC_TXDSRVTTGEN */
|
||||
0x00000000 /* EMC_FBIO_SPARE */
|
||||
0x00000042 /* EMC_ZCAL_WAIT_CNT */
|
||||
0x000e000e /* EMC_MRS_WAIT_CNT2 */
|
||||
0x00000000 /* EMC_CTT */
|
||||
0x00000003 /* EMC_CTT_DURATION */
|
||||
0x0000f2f3 /* EMC_CFG_PIPE */
|
||||
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
|
||||
0x0000000a /* EMC_QPOP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 (and later) SoC Memory Controller
|
||||
|
||||
maintainers:
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |
|
||||
The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
|
||||
into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
|
||||
handles memory requests for 40-bit virtual addresses from internal clients
|
||||
and arbitrates among them to allocate memory bandwidth.
|
||||
|
||||
Up to 15 GiB of physical memory can be supported. Security features such as
|
||||
encryption of traffic to and from DRAM via general security apertures are
|
||||
available for video and other secure applications, as well as DRAM ECC for
|
||||
automotive safety applications (single bit error correction and double bit
|
||||
error detection).
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^memory-controller@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- nvidia,tegra186-mc
|
||||
- nvidia,tegra194-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 2
|
||||
|
||||
ranges: true
|
||||
|
||||
dma-ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^external-memory-controller@[0-9a-f]+$":
|
||||
description:
|
||||
The bulk of the work involved in controlling the external memory
|
||||
controller on NVIDIA Tegra186 and later is performed on the BPMP. This
|
||||
coprocessor exposes the EMC clock that is used to set the frequency at
|
||||
which the external memory is clocked and a remote procedure call that
|
||||
can be used to obtain the set of available frequencies.
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- nvidia,tegra186-emc
|
||||
- nvidia,tegra194-emc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: external memory clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: emc
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the node representing the BPMP
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
memory-controller@2c00000 {
|
||||
compatible = "nvidia,tegra186-mc";
|
||||
reg = <0x0 0x02c00000 0x0 0xb0000>;
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>;
|
||||
|
||||
/*
|
||||
* Memory clients have access to all 40 bits that the memory
|
||||
* controller can address.
|
||||
*/
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
|
||||
|
||||
external-memory-controller@2c60000 {
|
||||
compatible = "nvidia,tegra186-emc";
|
||||
reg = <0x0 0x02c60000 0x0 0x50000>;
|
||||
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp: bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -108,4 +108,143 @@
|
|||
#define TEGRA186_SID_SE_VM6 0x4e
|
||||
#define TEGRA186_SID_SE_VM7 0x4f
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
|
||||
#define TEGRA186_MEMORY_CLIENT_PTCR 0x00
|
||||
/* PCIE reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e
|
||||
/* High-definition audio (HDA) reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_HDAR 0x15
|
||||
/* Host channel data reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16
|
||||
#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c
|
||||
/* SATA reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f
|
||||
/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27
|
||||
#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b
|
||||
/* PCIE writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_AFIW 0x31
|
||||
/* High-definition audio (HDA) writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_HDAW 0x35
|
||||
/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39
|
||||
/* SATA writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d
|
||||
/* ISP Read client for Crossbar A */
|
||||
#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44
|
||||
/* ISP Write client for Crossbar A */
|
||||
#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46
|
||||
/* ISP Write client Crossbar B */
|
||||
#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47
|
||||
/* XUSB reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a
|
||||
/* XUSB_HOST writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b
|
||||
/* XUSB reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c
|
||||
/* XUSB_DEV writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d
|
||||
/* TSEC Memory Return Data Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54
|
||||
/* TSEC Memory Write Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55
|
||||
/* 3D, ltcx reads instance 0 */
|
||||
#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58
|
||||
/* 3D, ltcx writes instance 0 */
|
||||
#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59
|
||||
/* sdmmca memory read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60
|
||||
/* sdmmcbmemory read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61
|
||||
/* sdmmc memory read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* sdmmca memory write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64
|
||||
/* sdmmcb memory write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65
|
||||
/* sdmmc memory write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c
|
||||
#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d
|
||||
/* VI Write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_VIW 0x72
|
||||
#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78
|
||||
#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79
|
||||
/* Audio Processing (APE) engine reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_APER 0x7a
|
||||
/* Audio Processing (APE) engine writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_APEW 0x7b
|
||||
#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e
|
||||
#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f
|
||||
/* SE Memory Return Data Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_SESRD 0x80
|
||||
/* SE Memory Write Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_SESWR 0x81
|
||||
/* ETR reads */
|
||||
#define TEGRA186_MEMORY_CLIENT_ETRR 0x84
|
||||
/* ETR writes */
|
||||
#define TEGRA186_MEMORY_CLIENT_ETRW 0x85
|
||||
/* TSECB Memory Return Data Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86
|
||||
/* TSECB Memory Write Client Description */
|
||||
#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87
|
||||
/* 3D, ltcx reads instance 1 */
|
||||
#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88
|
||||
/* 3D, ltcx writes instance 1 */
|
||||
#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89
|
||||
/* AXI Switch read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c
|
||||
/* AXI Switch write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d
|
||||
/* EQOS read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e
|
||||
/* EQOS write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f
|
||||
/* UFSHC read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90
|
||||
/* UFSHC write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91
|
||||
/* NVDISPLAY read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92
|
||||
/* BPMP read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94
|
||||
/* BPMPDMA read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95
|
||||
/* BPMPDMA write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96
|
||||
/* AON read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AONR 0x97
|
||||
/* AON write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AONW 0x98
|
||||
/* AONDMA read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99
|
||||
/* AONDMA write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a
|
||||
/* SCE read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SCER 0x9b
|
||||
/* SCE write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c
|
||||
/* SCEDMA read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d
|
||||
/* SCEDMA write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e
|
||||
/* APEDMA read client */
|
||||
#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f
|
||||
/* APEDMA write client */
|
||||
#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0
|
||||
/* NVDISPLAY read client instance 2 */
|
||||
#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1
|
||||
#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2
|
||||
#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,410 @@
|
|||
#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H
|
||||
#define DT_BINDINGS_MEMORY_TEGRA194_MC_H
|
||||
|
||||
/* special clients */
|
||||
#define TEGRA194_SID_INVALID 0x00
|
||||
#define TEGRA194_SID_PASSTHROUGH 0x7f
|
||||
|
||||
/* host1x clients */
|
||||
#define TEGRA194_SID_HOST1X 0x01
|
||||
#define TEGRA194_SID_CSI 0x02
|
||||
#define TEGRA194_SID_VIC 0x03
|
||||
#define TEGRA194_SID_VI 0x04
|
||||
#define TEGRA194_SID_ISP 0x05
|
||||
#define TEGRA194_SID_NVDEC 0x06
|
||||
#define TEGRA194_SID_NVENC 0x07
|
||||
#define TEGRA194_SID_NVJPG 0x08
|
||||
#define TEGRA194_SID_NVDISPLAY 0x09
|
||||
#define TEGRA194_SID_TSEC 0x0a
|
||||
#define TEGRA194_SID_TSECB 0x0b
|
||||
#define TEGRA194_SID_SE 0x0c
|
||||
#define TEGRA194_SID_SE1 0x0d
|
||||
#define TEGRA194_SID_SE2 0x0e
|
||||
#define TEGRA194_SID_SE3 0x0f
|
||||
|
||||
/* GPU clients */
|
||||
#define TEGRA194_SID_GPU 0x10
|
||||
|
||||
/* other SoC clients */
|
||||
#define TEGRA194_SID_AFI 0x11
|
||||
#define TEGRA194_SID_HDA 0x12
|
||||
#define TEGRA194_SID_ETR 0x13
|
||||
#define TEGRA194_SID_EQOS 0x14
|
||||
#define TEGRA194_SID_UFSHC 0x15
|
||||
#define TEGRA194_SID_AON 0x16
|
||||
#define TEGRA194_SID_SDMMC4 0x17
|
||||
#define TEGRA194_SID_SDMMC3 0x18
|
||||
#define TEGRA194_SID_SDMMC2 0x19
|
||||
#define TEGRA194_SID_SDMMC1 0x1a
|
||||
#define TEGRA194_SID_XUSB_HOST 0x1b
|
||||
#define TEGRA194_SID_XUSB_DEV 0x1c
|
||||
#define TEGRA194_SID_SATA 0x1d
|
||||
#define TEGRA194_SID_APE 0x1e
|
||||
#define TEGRA194_SID_SCE 0x1f
|
||||
|
||||
/* GPC DMA clients */
|
||||
#define TEGRA194_SID_GPCDMA_0 0x20
|
||||
#define TEGRA194_SID_GPCDMA_1 0x21
|
||||
#define TEGRA194_SID_GPCDMA_2 0x22
|
||||
#define TEGRA194_SID_GPCDMA_3 0x23
|
||||
#define TEGRA194_SID_GPCDMA_4 0x24
|
||||
#define TEGRA194_SID_GPCDMA_5 0x25
|
||||
#define TEGRA194_SID_GPCDMA_6 0x26
|
||||
#define TEGRA194_SID_GPCDMA_7 0x27
|
||||
|
||||
/* APE DMA clients */
|
||||
#define TEGRA194_SID_APE_1 0x28
|
||||
#define TEGRA194_SID_APE_2 0x29
|
||||
|
||||
/* camera RTCPU */
|
||||
#define TEGRA194_SID_RCE 0x2a
|
||||
|
||||
/* camera RTCPU on host1x address space */
|
||||
#define TEGRA194_SID_RCE_1X 0x2b
|
||||
|
||||
/* APE DMA clients */
|
||||
#define TEGRA194_SID_APE_3 0x2c
|
||||
|
||||
/* camera RTCPU running on APE */
|
||||
#define TEGRA194_SID_APE_CAM 0x2d
|
||||
#define TEGRA194_SID_APE_CAM_1X 0x2e
|
||||
|
||||
#define TEGRA194_SID_RCE_RM 0x2f
|
||||
#define TEGRA194_SID_VI_FALCON 0x30
|
||||
#define TEGRA194_SID_ISP_FALCON 0x31
|
||||
|
||||
/*
|
||||
* The BPMP has its SID value hardcoded in the firmware. Changing it requires
|
||||
* considerable effort.
|
||||
*/
|
||||
#define TEGRA194_SID_BPMP 0x32
|
||||
|
||||
/* for SMMU tests */
|
||||
#define TEGRA194_SID_SMMU_TEST 0x33
|
||||
|
||||
/* host1x virtualization channels */
|
||||
#define TEGRA194_SID_HOST1X_CTX0 0x38
|
||||
#define TEGRA194_SID_HOST1X_CTX1 0x39
|
||||
#define TEGRA194_SID_HOST1X_CTX2 0x3a
|
||||
#define TEGRA194_SID_HOST1X_CTX3 0x3b
|
||||
#define TEGRA194_SID_HOST1X_CTX4 0x3c
|
||||
#define TEGRA194_SID_HOST1X_CTX5 0x3d
|
||||
#define TEGRA194_SID_HOST1X_CTX6 0x3e
|
||||
#define TEGRA194_SID_HOST1X_CTX7 0x3f
|
||||
|
||||
/* host1x command buffers */
|
||||
#define TEGRA194_SID_HOST1X_VM0 0x40
|
||||
#define TEGRA194_SID_HOST1X_VM1 0x41
|
||||
#define TEGRA194_SID_HOST1X_VM2 0x42
|
||||
#define TEGRA194_SID_HOST1X_VM3 0x43
|
||||
#define TEGRA194_SID_HOST1X_VM4 0x44
|
||||
#define TEGRA194_SID_HOST1X_VM5 0x45
|
||||
#define TEGRA194_SID_HOST1X_VM6 0x46
|
||||
#define TEGRA194_SID_HOST1X_VM7 0x47
|
||||
|
||||
/* SE data buffers */
|
||||
#define TEGRA194_SID_SE_VM0 0x48
|
||||
#define TEGRA194_SID_SE_VM1 0x49
|
||||
#define TEGRA194_SID_SE_VM2 0x4a
|
||||
#define TEGRA194_SID_SE_VM3 0x4b
|
||||
#define TEGRA194_SID_SE_VM4 0x4c
|
||||
#define TEGRA194_SID_SE_VM5 0x4d
|
||||
#define TEGRA194_SID_SE_VM6 0x4e
|
||||
#define TEGRA194_SID_SE_VM7 0x4f
|
||||
|
||||
#define TEGRA194_SID_MIU 0x50
|
||||
|
||||
#define TEGRA194_SID_NVDLA0 0x51
|
||||
#define TEGRA194_SID_NVDLA1 0x52
|
||||
|
||||
#define TEGRA194_SID_PVA0 0x53
|
||||
#define TEGRA194_SID_PVA1 0x54
|
||||
#define TEGRA194_SID_NVENC1 0x55
|
||||
#define TEGRA194_SID_PCIE0 0x56
|
||||
#define TEGRA194_SID_PCIE1 0x57
|
||||
#define TEGRA194_SID_PCIE2 0x58
|
||||
#define TEGRA194_SID_PCIE3 0x59
|
||||
#define TEGRA194_SID_PCIE4 0x5a
|
||||
#define TEGRA194_SID_PCIE5 0x5b
|
||||
#define TEGRA194_SID_NVDEC1 0x5c
|
||||
|
||||
#define TEGRA194_SID_XUSB_VF0 0x5d
|
||||
#define TEGRA194_SID_XUSB_VF1 0x5e
|
||||
#define TEGRA194_SID_XUSB_VF2 0x5f
|
||||
#define TEGRA194_SID_XUSB_VF3 0x60
|
||||
|
||||
#define TEGRA194_SID_RCE_VM3 0x61
|
||||
#define TEGRA194_SID_VI_VM2 0x62
|
||||
#define TEGRA194_SID_VI_VM3 0x63
|
||||
#define TEGRA194_SID_RCE_SERVER 0x64
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
|
||||
#define TEGRA194_MEMORY_CLIENT_PTCR 0x00
|
||||
/* MSS internal memqual MIU7 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01
|
||||
/* MSS internal memqual MIU7 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02
|
||||
/* High-definition audio (HDA) read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HDAR 0x15
|
||||
/* Host channel data read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c
|
||||
/* SATA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f
|
||||
/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b
|
||||
/* High-definition audio (HDA) write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HDAW 0x35
|
||||
/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39
|
||||
/* SATA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d
|
||||
/* ISP read client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44
|
||||
/* ISP read client 1 for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45
|
||||
/* ISP Write client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46
|
||||
/* ISP Write client Crossbar B */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47
|
||||
/* XUSB_HOST read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a
|
||||
/* XUSB_HOST write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b
|
||||
/* XUSB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c
|
||||
/* XUSB_DEV write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d
|
||||
/* sdmmca memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60
|
||||
/* sdmmc memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* sdmmca memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64
|
||||
/* sdmmc memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d
|
||||
/* VI Write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIW 0x72
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79
|
||||
/* Audio Processing (APE) engine read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_APER 0x7a
|
||||
/* Audio Processing (APE) engine write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEW 0x7b
|
||||
#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e
|
||||
#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f
|
||||
/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82
|
||||
/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83
|
||||
/* ETR read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_ETRR 0x84
|
||||
/* ETR write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_ETRW 0x85
|
||||
/* AXI Switch read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c
|
||||
/* AXI Switch write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d
|
||||
/* EQOS read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e
|
||||
/* EQOS write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f
|
||||
/* UFSHC read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90
|
||||
/* UFSHC write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91
|
||||
/* NVDISPLAY read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92
|
||||
/* BPMP read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94
|
||||
/* BPMPDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95
|
||||
/* BPMPDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96
|
||||
/* AON read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONR 0x97
|
||||
/* AON write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONW 0x98
|
||||
/* AONDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99
|
||||
/* AONDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a
|
||||
/* SCE read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCER 0x9b
|
||||
/* SCE write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c
|
||||
/* SCEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d
|
||||
/* SCEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e
|
||||
/* APEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f
|
||||
/* APEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0
|
||||
/* NVDISPLAY read client instance 2 */
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3
|
||||
/* MSS internal memqual MIU0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6
|
||||
/* MSS internal memqual MIU0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7
|
||||
/* MSS internal memqual MIU1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8
|
||||
/* MSS internal memqual MIU1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9
|
||||
/* MSS internal memqual MIU2 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae
|
||||
/* MSS internal memqual MIU2 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf
|
||||
/* MSS internal memqual MIU3 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0
|
||||
/* MSS internal memqual MIU3 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1
|
||||
/* MSS internal memqual MIU4 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2
|
||||
/* MSS internal memqual MIU4 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3
|
||||
#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4
|
||||
#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb
|
||||
/* VI FLACON read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc
|
||||
/* VIFAL write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd
|
||||
/* DLA0ARDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe
|
||||
/* DLA0 Falcon read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf
|
||||
/* DLA0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0
|
||||
/* DLA0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1
|
||||
/* DLA1ARDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2
|
||||
/* DLA1 Falcon read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3
|
||||
/* DLA1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4
|
||||
/* DLA1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5
|
||||
/* PVA0RDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6
|
||||
/* PVA0RDB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7
|
||||
/* PVA0RDC read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8
|
||||
/* PVA0WRA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9
|
||||
/* PVA0WRB write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca
|
||||
/* PVA0WRC write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb
|
||||
/* PVA1RDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc
|
||||
/* PVA1RDB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd
|
||||
/* PVA1RDC read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce
|
||||
/* PVA1WRA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf
|
||||
/* PVA1WRB write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0
|
||||
/* PVA1WRC write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1
|
||||
/* RCE read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCER 0xd2
|
||||
/* RCE write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3
|
||||
/* RCEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4
|
||||
/* RCEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7
|
||||
/* PCIE0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8
|
||||
/* PCIE0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9
|
||||
/* PCIE1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda
|
||||
/* PCIE1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb
|
||||
/* PCIE2 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc
|
||||
/* PCIE2 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd
|
||||
/* PCIE3 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde
|
||||
/* PCIE3 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf
|
||||
/* PCIE4 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0
|
||||
/* PCIE4 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1
|
||||
/* PCIE5 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2
|
||||
/* PCIE5 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3
|
||||
/* ISP read client 1 for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8
|
||||
/* DLA0ARDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9
|
||||
/* DLA1ARDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea
|
||||
/* PVA0RDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb
|
||||
/* PVA0RDB1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec
|
||||
/* PVA1RDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed
|
||||
/* PVA1RDB1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee
|
||||
/* PCIE5r1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1
|
||||
/* ISP read client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2
|
||||
/* PCIE0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb
|
||||
/* MSS internal memqual MIU5 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc
|
||||
/* MSS internal memqual MIU5 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd
|
||||
/* MSS internal memqual MIU6 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe
|
||||
/* MSS internal memqual MIU6 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue