cxl/core: Define a 'struct cxl_switch_decoder'
Currently 'struct cxl_decoder' contains the superset of attributes needed for all decoder types. Before more type-specific attributes are added to the common definition, reorganize 'struct cxl_decoder' into type specific objects. This patch, the first of three, factors out a cxl_switch_decoder type. See the new kdoc for what a 'struct cxl_switch_decoder' represents in a CXL topology. Co-developed-by: Ben Widawsky <bwidawsk@kernel.org> Signed-off-by: Ben Widawsky <bwidawsk@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/165784325340.1758207.5064717153608954960.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
6b625b2bb8
commit
e636479e2f
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@ -81,6 +81,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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int target_map[CXL_DECODER_MAX_INTERLEAVE];
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struct cxl_cfmws_context *ctx = arg;
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struct cxl_port *root_port = ctx->root_port;
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struct cxl_switch_decoder *cxlsd;
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struct device *dev = ctx->dev;
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struct acpi_cedt_cfmws *cfmws;
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struct cxl_decoder *cxld;
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@ -106,10 +107,11 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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for (i = 0; i < ways; i++)
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target_map[i] = cfmws->interleave_targets[i];
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cxld = cxl_root_decoder_alloc(root_port, ways);
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cxlsd = cxl_root_decoder_alloc(root_port, ways);
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if (IS_ERR(cxld))
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return 0;
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cxld = &cxlsd->cxld;
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cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld->target_type = CXL_DECODER_EXPANDER;
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cxld->hpa_range = (struct range) {
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@ -49,20 +49,20 @@ static int add_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
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*/
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int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
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{
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struct cxl_decoder *cxld;
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struct cxl_switch_decoder *cxlsd;
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struct cxl_dport *dport;
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int single_port_map[1];
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cxld = cxl_switch_decoder_alloc(port, 1);
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if (IS_ERR(cxld))
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return PTR_ERR(cxld);
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cxlsd = cxl_switch_decoder_alloc(port, 1);
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if (IS_ERR(cxlsd))
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return PTR_ERR(cxlsd);
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device_lock_assert(&port->dev);
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dport = list_first_entry(&port->dports, typeof(*dport), list);
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single_port_map[0] = dport->port_id;
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return add_hdm_decoder(port, cxld, single_port_map);
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return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
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@ -255,14 +255,23 @@ int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
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int rc, target_count = cxlhdm->target_count;
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struct cxl_decoder *cxld;
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if (is_cxl_endpoint(port))
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if (is_cxl_endpoint(port)) {
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cxld = cxl_endpoint_decoder_alloc(port);
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else
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cxld = cxl_switch_decoder_alloc(port, target_count);
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if (IS_ERR(cxld)) {
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dev_warn(&port->dev,
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"Failed to allocate the decoder\n");
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return PTR_ERR(cxld);
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if (IS_ERR(cxld)) {
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dev_warn(&port->dev,
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"Failed to allocate the decoder\n");
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return PTR_ERR(cxld);
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}
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} else {
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struct cxl_switch_decoder *cxlsd;
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cxlsd = cxl_switch_decoder_alloc(port, target_count);
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if (IS_ERR(cxlsd)) {
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dev_warn(&port->dev,
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"Failed to allocate the decoder\n");
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return PTR_ERR(cxlsd);
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}
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cxld = &cxlsd->cxld;
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}
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rc = init_hdm_decoder(port, cxld, target_map, hdm, i);
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@ -120,20 +120,21 @@ static ssize_t target_type_show(struct device *dev,
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}
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static DEVICE_ATTR_RO(target_type);
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static ssize_t emit_target_list(struct cxl_decoder *cxld, char *buf)
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static ssize_t emit_target_list(struct cxl_switch_decoder *cxlsd, char *buf)
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{
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struct cxl_decoder *cxld = &cxlsd->cxld;
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ssize_t offset = 0;
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int i, rc = 0;
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for (i = 0; i < cxld->interleave_ways; i++) {
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struct cxl_dport *dport = cxld->target[i];
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struct cxl_dport *dport = cxlsd->target[i];
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struct cxl_dport *next = NULL;
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if (!dport)
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break;
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if (i + 1 < cxld->interleave_ways)
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next = cxld->target[i + 1];
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next = cxlsd->target[i + 1];
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rc = sysfs_emit_at(buf, offset, "%d%s", dport->port_id,
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next ? "," : "");
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if (rc < 0)
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@ -144,18 +145,20 @@ static ssize_t emit_target_list(struct cxl_decoder *cxld, char *buf)
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return offset;
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}
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static struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
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static ssize_t target_list_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct cxl_decoder *cxld = to_cxl_decoder(dev);
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struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(dev);
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ssize_t offset;
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unsigned int seq;
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int rc;
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do {
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seq = read_seqbegin(&cxld->target_lock);
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rc = emit_target_list(cxld, buf);
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} while (read_seqretry(&cxld->target_lock, seq));
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seq = read_seqbegin(&cxlsd->target_lock);
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rc = emit_target_list(cxlsd, buf);
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} while (read_seqretry(&cxlsd->target_lock, seq));
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if (rc < 0)
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return rc;
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@ -233,14 +236,28 @@ static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {
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NULL,
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};
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static void __cxl_decoder_release(struct cxl_decoder *cxld)
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{
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struct cxl_port *port = to_cxl_port(cxld->dev.parent);
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ida_free(&port->decoder_ida, cxld->id);
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put_device(&port->dev);
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}
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static void cxl_decoder_release(struct device *dev)
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{
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struct cxl_decoder *cxld = to_cxl_decoder(dev);
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struct cxl_port *port = to_cxl_port(dev->parent);
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ida_free(&port->decoder_ida, cxld->id);
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__cxl_decoder_release(cxld);
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kfree(cxld);
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put_device(&port->dev);
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}
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static void cxl_switch_decoder_release(struct device *dev)
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{
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struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(dev);
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__cxl_decoder_release(&cxlsd->cxld);
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kfree(cxlsd);
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}
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static const struct device_type cxl_decoder_endpoint_type = {
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@ -251,13 +268,13 @@ static const struct device_type cxl_decoder_endpoint_type = {
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static const struct device_type cxl_decoder_switch_type = {
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.name = "cxl_decoder_switch",
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.release = cxl_decoder_release,
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.release = cxl_switch_decoder_release,
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.groups = cxl_decoder_switch_attribute_groups,
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};
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static const struct device_type cxl_decoder_root_type = {
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.name = "cxl_decoder_root",
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.release = cxl_decoder_release,
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.release = cxl_switch_decoder_release,
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.groups = cxl_decoder_root_attribute_groups,
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};
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@ -272,15 +289,29 @@ bool is_root_decoder(struct device *dev)
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}
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EXPORT_SYMBOL_NS_GPL(is_root_decoder, CXL);
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static bool is_switch_decoder(struct device *dev)
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{
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return is_root_decoder(dev) || dev->type == &cxl_decoder_switch_type;
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}
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struct cxl_decoder *to_cxl_decoder(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, dev->type->release != cxl_decoder_release,
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if (dev_WARN_ONCE(dev,
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!is_switch_decoder(dev) && !is_endpoint_decoder(dev),
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"not a cxl_decoder device\n"))
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return NULL;
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return container_of(dev, struct cxl_decoder, dev);
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_decoder, CXL);
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static struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, !is_switch_decoder(dev),
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"not a cxl_switch_decoder device\n"))
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return NULL;
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return container_of(dev, struct cxl_switch_decoder, cxld.dev);
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}
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static void cxl_ep_release(struct cxl_ep *ep)
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{
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if (!ep)
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@ -1146,7 +1177,7 @@ struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
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}
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EXPORT_SYMBOL_NS_GPL(cxl_find_dport_by_dev, CXL);
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static int decoder_populate_targets(struct cxl_decoder *cxld,
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static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
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struct cxl_port *port, int *target_map)
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{
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int i, rc = 0;
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@ -1159,17 +1190,17 @@ static int decoder_populate_targets(struct cxl_decoder *cxld,
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if (list_empty(&port->dports))
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return -EINVAL;
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write_seqlock(&cxld->target_lock);
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for (i = 0; i < cxld->nr_targets; i++) {
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write_seqlock(&cxlsd->target_lock);
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for (i = 0; i < cxlsd->nr_targets; i++) {
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struct cxl_dport *dport = find_dport(port, target_map[i]);
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if (!dport) {
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rc = -ENXIO;
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break;
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}
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cxld->target[i] = dport;
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cxlsd->target[i] = dport;
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}
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write_sequnlock(&cxld->target_lock);
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write_sequnlock(&cxlsd->target_lock);
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return rc;
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}
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@ -1177,56 +1208,34 @@ static int decoder_populate_targets(struct cxl_decoder *cxld,
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static struct lock_class_key cxl_decoder_key;
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/**
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* cxl_decoder_alloc - Allocate a new CXL decoder
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* cxl_decoder_init - Common decoder setup / initialization
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* @port: owning port of this decoder
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* @nr_targets: downstream targets accessible by this decoder. All upstream
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* ports and root ports must have at least 1 target. Endpoint
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* devices will have 0 targets. Callers wishing to register an
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* endpoint device should specify 0.
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* @cxld: common decoder properties to initialize
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*
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* A port should contain one or more decoders. Each of those decoders enable
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* some address space for CXL.mem utilization. A decoder is expected to be
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* configured by the caller before registering.
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*
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* Return: A new cxl decoder to be registered by cxl_decoder_add(). The decoder
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* is initialized to be a "passthrough" decoder.
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* A port may contain one or more decoders. Each of those decoders
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* enable some address space for CXL.mem utilization. A decoder is
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* expected to be configured by the caller before registering via
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* cxl_decoder_add()
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*/
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static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets)
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static int cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)
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{
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struct cxl_decoder *cxld;
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struct device *dev;
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int rc = 0;
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if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
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return ERR_PTR(-EINVAL);
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cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
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if (!cxld)
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return ERR_PTR(-ENOMEM);
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int rc;
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rc = ida_alloc(&port->decoder_ida, GFP_KERNEL);
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if (rc < 0)
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goto err;
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return rc;
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/* need parent to stick around to release the id */
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get_device(&port->dev);
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cxld->id = rc;
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cxld->nr_targets = nr_targets;
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seqlock_init(&cxld->target_lock);
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dev = &cxld->dev;
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device_initialize(dev);
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lockdep_set_class(&dev->mutex, &cxl_decoder_key);
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device_set_pm_not_required(dev);
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dev->parent = &port->dev;
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dev->bus = &cxl_bus_type;
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if (is_cxl_root(port))
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cxld->dev.type = &cxl_decoder_root_type;
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else if (is_cxl_endpoint(port))
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cxld->dev.type = &cxl_decoder_endpoint_type;
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else
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cxld->dev.type = &cxl_decoder_switch_type;
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/* Pre initialize an "empty" decoder */
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cxld->interleave_ways = 1;
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@ -1237,10 +1246,19 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
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.end = -1,
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};
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return cxld;
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err:
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kfree(cxld);
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return ERR_PTR(rc);
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return 0;
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}
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static int cxl_switch_decoder_init(struct cxl_port *port,
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struct cxl_switch_decoder *cxlsd,
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int nr_targets)
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{
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if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
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return -EINVAL;
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cxlsd->nr_targets = nr_targets;
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seqlock_init(&cxlsd->target_lock);
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return cxl_decoder_init(port, &cxlsd->cxld);
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}
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/**
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@ -1253,13 +1271,29 @@ err:
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* firmware description of CXL resources into a CXL standard decode
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* topology.
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*/
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struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets)
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struct cxl_switch_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets)
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{
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struct cxl_switch_decoder *cxlsd;
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struct cxl_decoder *cxld;
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int rc;
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if (!is_cxl_root(port))
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return ERR_PTR(-EINVAL);
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return cxl_decoder_alloc(port, nr_targets);
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cxlsd = kzalloc(struct_size(cxlsd, target, nr_targets), GFP_KERNEL);
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if (!cxlsd)
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return ERR_PTR(-ENOMEM);
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rc = cxl_switch_decoder_init(port, cxlsd, nr_targets);
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if (rc) {
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kfree(cxlsd);
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return ERR_PTR(rc);
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}
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cxld = &cxlsd->cxld;
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cxld->dev.type = &cxl_decoder_root_type;
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return cxlsd;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL);
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@ -1274,13 +1308,29 @@ EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL);
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* that sit between Switch Upstream Ports / Switch Downstream Ports and
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* Host Bridges / Root Ports.
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*/
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struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets)
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struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
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unsigned int nr_targets)
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{
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struct cxl_switch_decoder *cxlsd;
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struct cxl_decoder *cxld;
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int rc;
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if (is_cxl_root(port) || is_cxl_endpoint(port))
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return ERR_PTR(-EINVAL);
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return cxl_decoder_alloc(port, nr_targets);
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cxlsd = kzalloc(struct_size(cxlsd, target, nr_targets), GFP_KERNEL);
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if (!cxlsd)
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return ERR_PTR(-ENOMEM);
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rc = cxl_switch_decoder_init(port, cxlsd, nr_targets);
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if (rc) {
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kfree(cxlsd);
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return ERR_PTR(rc);
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}
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cxld = &cxlsd->cxld;
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cxld->dev.type = &cxl_decoder_switch_type;
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return cxlsd;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
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@ -1292,16 +1342,30 @@ EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
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*/
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struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port)
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{
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struct cxl_decoder *cxld;
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int rc;
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if (!is_cxl_endpoint(port))
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return ERR_PTR(-EINVAL);
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return cxl_decoder_alloc(port, 0);
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cxld = kzalloc(sizeof(*cxld), GFP_KERNEL);
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if (!cxld)
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return ERR_PTR(-ENOMEM);
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rc = cxl_decoder_init(port, cxld);
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if (rc) {
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kfree(cxld);
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return ERR_PTR(rc);
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}
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cxld->dev.type = &cxl_decoder_endpoint_type;
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return cxld;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
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/**
|
||||
* cxl_decoder_add_locked - Add a decoder with targets
|
||||
* @cxld: The cxl decoder allocated by cxl_decoder_alloc()
|
||||
* @cxld: The cxl decoder allocated by cxl_<type>_decoder_alloc()
|
||||
* @target_map: A list of downstream ports that this decoder can direct memory
|
||||
* traffic to. These numbers should correspond with the port number
|
||||
* in the PCIe Link Capabilities structure.
|
||||
|
|
@ -1337,7 +1401,9 @@ int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map)
|
|||
|
||||
port = to_cxl_port(cxld->dev.parent);
|
||||
if (!is_endpoint_decoder(dev)) {
|
||||
rc = decoder_populate_targets(cxld, port, target_map);
|
||||
struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(dev);
|
||||
|
||||
rc = decoder_populate_targets(cxlsd, port, target_map);
|
||||
if (rc && (cxld->flags & CXL_DECODER_F_ENABLE)) {
|
||||
dev_err(&port->dev,
|
||||
"Failed to populate active decoder targets\n");
|
||||
|
|
@ -1355,7 +1421,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_decoder_add_locked, CXL);
|
|||
|
||||
/**
|
||||
* cxl_decoder_add - Add a decoder with targets
|
||||
* @cxld: The cxl decoder allocated by cxl_decoder_alloc()
|
||||
* @cxld: The cxl decoder allocated by cxl_<type>_decoder_alloc()
|
||||
* @target_map: A list of downstream ports that this decoder can direct memory
|
||||
* traffic to. These numbers should correspond with the port number
|
||||
* in the PCIe Link Capabilities structure.
|
||||
|
|
|
|||
|
|
@ -220,7 +220,7 @@ enum cxl_decoder_type {
|
|||
#define CXL_DECODER_MAX_INTERLEAVE 16
|
||||
|
||||
/**
|
||||
* struct cxl_decoder - CXL address range decode configuration
|
||||
* struct cxl_decoder - Common CXL HDM Decoder Attributes
|
||||
* @dev: this decoder's device
|
||||
* @id: kernel device name id
|
||||
* @hpa_range: Host physical address range mapped by this decoder
|
||||
|
|
@ -228,9 +228,6 @@ enum cxl_decoder_type {
|
|||
* @interleave_granularity: data stride per dport
|
||||
* @target_type: accelerator vs expander (type2 vs type3) selector
|
||||
* @flags: memory type capabilities and locking
|
||||
* @target_lock: coordinate coherent reads of the target list
|
||||
* @nr_targets: number of elements in @target
|
||||
* @target: active ordered target list in current decoder configuration
|
||||
*/
|
||||
struct cxl_decoder {
|
||||
struct device dev;
|
||||
|
|
@ -240,6 +237,23 @@ struct cxl_decoder {
|
|||
int interleave_granularity;
|
||||
enum cxl_decoder_type target_type;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cxl_switch_decoder - Switch specific CXL HDM Decoder
|
||||
* @cxld: base cxl_decoder object
|
||||
* @target_lock: coordinate coherent reads of the target list
|
||||
* @nr_targets: number of elements in @target
|
||||
* @target: active ordered target list in current decoder configuration
|
||||
*
|
||||
* The 'switch' decoder type represents the decoder instances of cxl_port's that
|
||||
* route from the root of a CXL memory decode topology to the endpoints. They
|
||||
* come in two flavors, root-level decoders, statically defined by platform
|
||||
* firmware, and mid-level decoders, where interleave-granularity,
|
||||
* interleave-width, and the target list are mutable.
|
||||
*/
|
||||
struct cxl_switch_decoder {
|
||||
struct cxl_decoder cxld;
|
||||
seqlock_t target_lock;
|
||||
int nr_targets;
|
||||
struct cxl_dport *target[];
|
||||
|
|
@ -371,10 +385,10 @@ struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
|
|||
struct cxl_decoder *to_cxl_decoder(struct device *dev);
|
||||
bool is_root_decoder(struct device *dev);
|
||||
bool is_endpoint_decoder(struct device *dev);
|
||||
struct cxl_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
|
||||
unsigned int nr_targets);
|
||||
struct cxl_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
|
||||
unsigned int nr_targets);
|
||||
struct cxl_switch_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
|
||||
unsigned int nr_targets);
|
||||
struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
|
||||
unsigned int nr_targets);
|
||||
int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
|
||||
struct cxl_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
|
||||
int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
|
||||
|
|
|
|||
|
|
@ -451,14 +451,23 @@ static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
|
|||
struct cxl_decoder *cxld;
|
||||
int rc;
|
||||
|
||||
if (target_count)
|
||||
cxld = cxl_switch_decoder_alloc(port, target_count);
|
||||
else
|
||||
if (target_count) {
|
||||
struct cxl_switch_decoder *cxlsd;
|
||||
|
||||
cxlsd = cxl_switch_decoder_alloc(port, target_count);
|
||||
if (IS_ERR(cxlsd)) {
|
||||
dev_warn(&port->dev,
|
||||
"Failed to allocate the decoder\n");
|
||||
return PTR_ERR(cxlsd);
|
||||
}
|
||||
cxld = &cxlsd->cxld;
|
||||
} else {
|
||||
cxld = cxl_endpoint_decoder_alloc(port);
|
||||
if (IS_ERR(cxld)) {
|
||||
dev_warn(&port->dev,
|
||||
"Failed to allocate the decoder\n");
|
||||
return PTR_ERR(cxld);
|
||||
if (IS_ERR(cxld)) {
|
||||
dev_warn(&port->dev,
|
||||
"Failed to allocate the decoder\n");
|
||||
return PTR_ERR(cxld);
|
||||
}
|
||||
}
|
||||
|
||||
cxld->hpa_range = (struct range) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue