dt-bindings: remoteproc: qcom: Replace halt-nav with spare-regs
7C retail devices using MSA based boot will result in a fuse combination which will prevent accesses to MSS PERPH register space where the mpss clocks and halt-nav reside. However accesses to conn_box_spare0 in TCSR register space is still permitted so rename the binding appropriately to qcom,spare-regs and drop all accesses to the MPSS PERPH register space. Tested-by: Evan Green <evgreen@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200415145110.20624-2-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -79,7 +79,7 @@ on the Qualcomm Hexagon core.
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"snoc_axi", "mnoc_axi", "qdss"
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qcom,sc7180-mss-pil:
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must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi",
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"mss_crypto", "mss_nav", "nav"
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"nav"
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qcom,sdm845-mss-pil:
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must be "iface", "bus", "mem", "xo", "gpll0_mss",
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"snoc_axi", "mnoc_axi", "prng"
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@ -181,16 +181,12 @@ For the compatible string below the following supplies are required:
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For the compatible strings below the following phandle references are required:
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"qcom,sc7180-mss-pil"
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- qcom,halt-nav-regs:
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- qcom,spare-regs:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to a list of 2 phandles with one offset each for
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the modem sub-system running on SC7180 SoC. The first
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phandle reference is to the mss clock node followed by the
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offset within register space for nav halt register. The
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second phandle reference is to a syscon representing TCSR
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followed by the offset within syscon for conn_box_spare0
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register.
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Definition: a phandle reference to a syscon representing TCSR followed
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by the offset within syscon for conn_box_spare0 register
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used by the modem sub-system running on SC7180 SoC.
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= SUBNODES:
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The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
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