pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcd
("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
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@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
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mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
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mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
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mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
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mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
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mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
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mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
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mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
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mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
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mpp12 12 gpio, dev(a1), audio(bclk)
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mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
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@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
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MPP_FUNCTION(0x5, "nand", "ce")),
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MPP_MODE(9,
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MPP_FUNCTION(0x0, "gpio", NULL),
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MPP_FUNCTION(0x1, "nf", "wen"),
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MPP_FUNCTION(0x2, "spi0", "sck"),
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MPP_FUNCTION(0x3, "spi1", "sck"),
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MPP_FUNCTION(0x5, "nand", "we")),
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MPP_MODE(10,
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MPP_FUNCTION(0x0, "gpio", NULL),
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MPP_FUNCTION(0x1, "nf", "ren"),
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MPP_FUNCTION(0x2, "dram", "vttctrl"),
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MPP_FUNCTION(0x3, "led", "c1"),
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MPP_FUNCTION(0x5, "nand", "re"),
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