hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

USB: s3c-hsotg: Add support for external USB clock 

The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.

This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock definition

Signed-off-by: Maurus Cuelenaere <mcuelenaere@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Maurus Cuelenaere 2010-07-19 09:40:50 +01:00 committed by Greg Kroah-Hartman
parent a33e7136e9
commit e50bf385bf
1 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/usb/gadget/s3c-hsotg.c
View File

@ -25,6 +25,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/clk.h>
#include <linux/usb/ch9.h> #include <linux/usb/ch9.h>
#include <linux/usb/gadget.h> #include <linux/usb/gadget.h>
@ -2798,6 +2799,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
*/ */
static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
{ {
struct clk *xusbxti;
u32 osc; u32 osc;
writel(0, S3C_PHYPWR); writel(0, S3C_PHYPWR);
@ -2805,6 +2807,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0; osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
xusbxti = clk_get(hsotg->dev, "xusbxti");
if (xusbxti && !IS_ERR(xusbxti)) {
switch (clk_get_rate(xusbxti)) {
case 12*MHZ:
osc |= S3C_PHYCLK_CLKSEL_12M;
break;
case 24*MHZ:
osc |= S3C_PHYCLK_CLKSEL_24M;
break;
default:
case 48*MHZ:
/* default reference clock */
break;
}
clk_put(xusbxti);
}
writel(osc | 0x10, S3C_PHYCLK); writel(osc | 0x10, S3C_PHYCLK);
/* issue a full set of resets to the otg and core */ /* issue a full set of resets to the otg and core */