ARM: S5P6440: Remove usage of clk_h and add clk_hclk clock
The clk_h clock is of type 'struct clk' whereas on S5P6440, the hclk is more suitable to be of type 'struct clksrc_clk' (since hclk clock is divided version of armclk) This patch modifies the following. 1. Adds the 'clk_hclk' clock which is of type 'struct clksrc_clk'. 2. Removes all references to the clk_h clock. 3. Addes clk_hclk into the list of sysclks. 4. The clock rate 'hclk' is modified to be derived from clk_hclk. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -266,6 +266,15 @@ static struct clksrc_clk clk_dout_mpll = {
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
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};
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};
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static struct clksrc_clk clk_hclk = {
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.clk = {
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.name = "clk_hclk",
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.id = -1,
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.parent = &clk_armclk.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
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};
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int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
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int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
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{
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{
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unsigned long flags;
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unsigned long flags;
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@ -321,7 +330,7 @@ static struct clk init_clocks_disable[] = {
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{
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{
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.name = "nand",
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.name = "nand",
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.id = -1,
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.id = -1,
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.parent = &clk_h,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_mem_ctrl,
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.enable = s5p6440_mem_ctrl,
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.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
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.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
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}, {
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}, {
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@ -580,6 +589,7 @@ static struct clksrc_clk *sysclks[] = {
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&clk_mout_mpll,
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&clk_mout_mpll,
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&clk_dout_mpll,
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&clk_dout_mpll,
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&clk_armclk,
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&clk_armclk,
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&clk_hclk,
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};
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};
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void __init_or_cpufreq s5p6440_setup_clocks(void)
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void __init_or_cpufreq s5p6440_setup_clocks(void)
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@ -628,7 +638,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
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print_mhz(apll), print_mhz(mpll), print_mhz(epll));
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print_mhz(apll), print_mhz(mpll), print_mhz(epll));
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fclk = clk_get_rate(&clk_armclk.clk);
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fclk = clk_get_rate(&clk_armclk.clk);
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hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
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hclk = clk_get_rate(&clk_hclk.clk);
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pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
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pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
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if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
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if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
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