net: qlge: Eliminate duplicate barriers on weakly-ordered archs
Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Create a new wrapper function with relaxed write operator. Use the new wrapper when a write is following a wmb(). Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2184,6 +2184,22 @@ static inline void ql_write_db_reg(u32 val, void __iomem *addr)
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mmiowb();
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mmiowb();
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}
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}
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/*
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* Doorbell Registers:
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* Doorbell registers are virtual registers in the PCI memory space.
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* The space is allocated by the chip during PCI initialization. The
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* device driver finds the doorbell address in BAR 3 in PCI config space.
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* The registers are used to control outbound and inbound queues. For
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* example, the producer index for an outbound queue. Each queue uses
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* 1 4k chunk of memory. The lower half of the space is for outbound
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* queues. The upper half is for inbound queues.
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* Caller has to guarantee ordering.
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*/
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static inline void ql_write_db_reg_relaxed(u32 val, void __iomem *addr)
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{
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writel_relaxed(val, addr);
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}
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/*
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/*
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* Shadow Registers:
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* Shadow Registers:
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* Outbound queues have a consumer index that is maintained by the chip.
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* Outbound queues have a consumer index that is maintained by the chip.
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@ -2700,7 +2700,8 @@ static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
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tx_ring->prod_idx = 0;
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tx_ring->prod_idx = 0;
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wmb();
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wmb();
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ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
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ql_write_db_reg_relaxed(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
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mmiowb();
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netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
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netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
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"tx queued, slot %d, len %d\n",
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"tx queued, slot %d, len %d\n",
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tx_ring->prod_idx, skb->len);
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tx_ring->prod_idx, skb->len);
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