pinctrl: sh-pfc: Updates for v4.12 (take three)
- Miscellaneous fixes for R-Car M2-W and R-Car E2. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY/dpqAAoJEEgEtLw/Ve77EjwQAKBc9m89RAdQFxXdv/KFPFLz lMPnS+UroXClw7qr8f0yr3rdZJuHcdOyozCF0+ZiimKikBDBlKVqp5ywX1VcP0fx r5rR/naDEakMuJlzrbBEbYxzpi//xjJivjhYYDvTORE3FT+3Qlrlk/9ZyW5/53ST Mp+yvU8eK0hj/fUzfz0DEcfZVampyHcC4esO7dLWJhFyWCJIBBUD0PsL+hpzp0ll 4xf/pDP/ItxIOAS+c+IhxitGQi1mEe5wa+tf5CHdkFohKtHxVHvcT7UvWWqUgikN VTiDjKG1WPsT9Cl9pMEAu+zygozBKxnoaXZVCCh/negU/047aFFLLrR6uEL1PAwc vAcyDKH9gelMBZnjnYX2dP4qiu6nOsNgaxU0jWPCWpb87Jfp6R0KkfmfaCCHMqjm +SzZ1JdN+Tw1qJYjCFPvs6Eysqhne9ydv4FCByMOzLJxPq7p1WFC8khbud1NoRYJ 8q0UGNoQByWn44xroV0H51eYY3CbPTKdTufhWNY042wk/AGZJiRiku+bu8s0N6dU i7nTFBcI/SDq/P10iVkq2mIj/dK69bDovVHQw0pYTjqyvlM1NwePkr0kkhvgcgoD YxHaqC+D7lA4e1WB/OZppirWK4RiOHkFb6p9XaTiClJ6Ftc8jypq3bOiLl9dNsRl Ogs0f/EAZboiejemGHRU =IP75 -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.12-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take three) - Miscellaneous fixes for R-Car M2-W and R-Car E2.
This commit is contained in:
Linus Walleij
commit
e41f3207be
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@ -203,7 +203,7 @@ enum {
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/* IPSR6 */
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FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
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FN_SCIF_CLK, FN_BPFCLK_E,
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FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
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FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
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FN_SCIFA2_RXD, FN_FMIN_E,
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FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
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@ -573,7 +573,7 @@ enum {
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/* IPSR6 */
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AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
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SCIF_CLK_MARK, BPFCLK_E_MARK,
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SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
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AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
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SCIFA2_RXD_MARK, FMIN_E_MARK,
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AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
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@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
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PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
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PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
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PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
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PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
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PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
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PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
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PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
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PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
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PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
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PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
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PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
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PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
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PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
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PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
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PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
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PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
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@ -1090,6 +1093,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
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PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
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PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
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PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
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PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
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PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
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PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
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@ -1099,7 +1103,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
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PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
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PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
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PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
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PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
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PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
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PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
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PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
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@ -5707,7 +5711,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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},
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{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
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2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
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/* IP2_31_20 [2] */
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/* IP2_31_30 [2] */
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0, 0, 0, 0,
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/* IP2_29_27 [3] */
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FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
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@ -5727,7 +5731,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* IP2_15_13 [3] */
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FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
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0, 0, 0,
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/* IP2_12_0 [3] */
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/* IP2_12_10 [3] */
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FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
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0, 0, 0,
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/* IP2_9_7 [3] */
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@ -5896,7 +5900,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0,
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/* IP6_2_0 [3] */
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FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
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FN_SCIF_CLK, 0, FN_BPFCLK_E,
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FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
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0, 0, }
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},
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{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
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@ -6038,7 +6042,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* IP10_24_22 [3] */
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FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
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0, 0, 0,
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/* IP10_21_29 [3] */
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/* IP10_21_19 [3] */
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FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
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FN_TS_SDATA0_C, FN_ATACS11_N,
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0, 0, 0,
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@ -281,8 +281,8 @@ enum {
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FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
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FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
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FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
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FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
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FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
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FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
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FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
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/* IPSR13 */
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FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
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@ -575,8 +575,8 @@ enum {
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ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
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VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
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SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
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ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
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VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
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ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
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VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,
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/* IPSR13 */
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SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
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@ -1413,13 +1413,13 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
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PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
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PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
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PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
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PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
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PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
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PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
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PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
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PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
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PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
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PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
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PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
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PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
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/* IPSR13 */
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@ -4938,10 +4938,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, 0,
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/* IP12_29_27 [3] */
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FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
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FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
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FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
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/* IP12_26_24 [3] */
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FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
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FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
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FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
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/* IP12_23_21 [3] */
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FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
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FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
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