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Blackfin arch: fix bug NOR Flash MTD mount fail 

Config EBIU flash mode properly. EBIU_MODE EBIU_FCTL
EBIU_MBSCTL register should be configurd to Flash
mode.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Sonic Zhang 2007-11-21 23:49:52 +08:00 committed by Bryan Wu
parent 28a44d4bd6
commit e40540b304
2 changed files with 35 additions and 0 deletions
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14
arch/blackfin/Kconfig
View File

@ -866,6 +866,20 @@ config BANK_3
default 0x99B3 default 0x99B3
endmenu endmenu
config EBIU_MBSCTLVAL
hex "EBIU Bank Select Control Register"
depends on BF54x
default 0
config EBIU_MODEVAL
hex "Flash Memory Mode Control Register"
depends on BF54x
default 1
config EBIU_FCTLVAL
hex "Flash Memory Bank Control Register"
depends on BF54x
default 6
endmenu endmenu
############################################################################# #############################################################################

21
arch/blackfin/mach-bf548/head.S
View File

@ -158,6 +158,27 @@ ENTRY(__stext)
w[p2] = r0; w[p2] = r0;
ssync; ssync;
p2.h = hi(EBIU_MBSCTL);
p2.l = lo(EBIU_MBSCTL);
r0.h = hi(CONFIG_EBIU_MBSCTLVAL);
r0.l = lo(CONFIG_EBIU_MBSCTLVAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_MODE);
p2.l = lo(EBIU_MODE);
r0.h = hi(CONFIG_EBIU_MODEVAL);
r0.l = lo(CONFIG_EBIU_MODEVAL);
[p2] = r0;
ssync;
p2.h = hi(EBIU_FCTL);
p2.l = lo(EBIU_FCTL);
r0.h = hi(CONFIG_EBIU_FCTLVAL);
r0.l = lo(CONFIG_EBIU_FCTLVAL);
[p2] = r0;
ssync;
/* This section keeps the processor in supervisor mode /* This section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot. * during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation. * See page 3-9 of Hardware Reference manual for documentation.