usb: musb: core: fix TX/RX endpoint order
As per Mentor Graphics' documentation, we should always handle TX endpoints before RX endpoints. This patch fixes that error while also updating some hard-to-read comments which were scattered around musb_interrupt(). This patch should be backported as far back as possible since this error has been in the driver since it's conception. Cc: <stable@vger.kernel.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -1597,16 +1597,30 @@ irqreturn_t musb_interrupt(struct musb *musb)
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is_host_active(musb) ? "host" : "peripheral",
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musb->int_usb, musb->int_tx, musb->int_rx);
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/* the core can interrupt us for multiple reasons; docs have
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* a generic interrupt flowchart to follow
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/**
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* According to Mentor Graphics' documentation, flowchart on page 98,
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* IRQ should be handled as follows:
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*
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* . Resume IRQ
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* . Session Request IRQ
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* . VBUS Error IRQ
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* . Suspend IRQ
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* . Connect IRQ
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* . Disconnect IRQ
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* . Reset/Babble IRQ
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* . SOF IRQ (we're not using this one)
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* . Endpoint 0 IRQ
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* . TX Endpoints
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* . RX Endpoints
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*
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* We will be following that flowchart in order to avoid any problems
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* that might arise with internal Finite State Machine.
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*/
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if (musb->int_usb)
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retval |= musb_stage0_irq(musb, musb->int_usb,
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devctl);
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/* "stage 1" is handling endpoint irqs */
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/* handle endpoint 0 first */
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if (musb->int_tx & 1) {
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if (is_host_active(musb))
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retval |= musb_h_ep0_irq(musb);
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@ -1614,13 +1628,24 @@ irqreturn_t musb_interrupt(struct musb *musb)
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retval |= musb_g_ep0_irq(musb);
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}
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/* RX on endpoints 1-15 */
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reg = musb->int_tx >> 1;
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ep_num = 1;
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while (reg) {
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if (reg & 1) {
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retval = IRQ_HANDLED;
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if (is_host_active(musb))
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musb_host_tx(musb, ep_num);
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else
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musb_g_tx(musb, ep_num);
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}
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reg >>= 1;
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ep_num++;
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}
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reg = musb->int_rx >> 1;
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ep_num = 1;
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while (reg) {
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if (reg & 1) {
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/* musb_ep_select(musb->mregs, ep_num); */
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/* REVISIT just retval = ep->rx_irq(...) */
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retval = IRQ_HANDLED;
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if (is_host_active(musb))
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musb_host_rx(musb, ep_num);
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@ -1632,23 +1657,6 @@ irqreturn_t musb_interrupt(struct musb *musb)
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ep_num++;
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}
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/* TX on endpoints 1-15 */
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reg = musb->int_tx >> 1;
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ep_num = 1;
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while (reg) {
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if (reg & 1) {
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/* musb_ep_select(musb->mregs, ep_num); */
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/* REVISIT just retval |= ep->tx_irq(...) */
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retval = IRQ_HANDLED;
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if (is_host_active(musb))
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musb_host_tx(musb, ep_num);
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else
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musb_g_tx(musb, ep_num);
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}
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reg >>= 1;
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ep_num++;
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}
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return retval;
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}
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EXPORT_SYMBOL_GPL(musb_interrupt);
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