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pinctrl: uniphier: fix pin_config_get() for input-enable 

For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers.  So, the register offset must be
taken into account.  Otherwise, wrong input-enable status is displayed.

While we here, rename the macro because it is a base address.

Fixes: aa543888ca ("pinctrl: uniphier: support per-pin input enable for new SoCs")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Masahiro Yamada 2017-07-31 15:21:07 +09:00 committed by Linus Walleij
parent 9fc939c683
commit e3829d1546
1 changed files with 8 additions and 5 deletions
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13
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
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@ -32,7 +32,7 @@
#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
#define UNIPHIER_PINCTRL_IECTRL 0x1d00
#define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00
struct uniphier_pinctrl_priv {
struct pinctrl_desc pctldesc;
@ -252,18 +252,21 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
unsigned int val;
unsigned int reg, mask, val;
int ret;
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
/* This pin is always input-enabled. */
return 0;
ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
mask = BIT(iectrl % 32);
ret = regmap_read(priv->regmap, reg, &val);
if (ret)
return ret;
return val & BIT(iectrl) ? 0 : -EINVAL;
return val & mask ? 0 : -EINVAL;
}
static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
@ -456,7 +459,7 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
return enable ? 0 : -EINVAL;
reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4;
mask = BIT(iectrl % 32);
return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);