PCI: mobiveil: Reformat the code for readability
Reformat the code to make it more readable. No functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
This commit is contained in:
Hou Zhiqiang
Lorenzo Pieralisi
parent
93bad0f5d1
commit
e369faf625
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@ -31,38 +31,40 @@
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* translation tables are grouped into windows, each window registers are
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* grouped into blocks of 4 or 16 registers each
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*/
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#define PAB_REG_BLOCK_SIZE 16
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#define PAB_EXT_REG_BLOCK_SIZE 4
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#define PAB_REG_BLOCK_SIZE 16
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#define PAB_EXT_REG_BLOCK_SIZE 4
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#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
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#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
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#define PAB_REG_ADDR(offset, win) \
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(offset + (win * PAB_REG_BLOCK_SIZE))
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#define PAB_EXT_REG_ADDR(offset, win) \
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(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
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#define LTSSM_STATUS 0x0404
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#define LTSSM_STATUS_L0_MASK 0x3f
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#define LTSSM_STATUS_L0 0x2d
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#define LTSSM_STATUS 0x0404
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#define LTSSM_STATUS_L0_MASK 0x3f
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#define LTSSM_STATUS_L0 0x2d
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#define PAB_CTRL 0x0808
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#define AMBA_PIO_ENABLE_SHIFT 0
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#define PEX_PIO_ENABLE_SHIFT 1
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#define PAGE_SEL_SHIFT 13
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#define PAGE_SEL_MASK 0x3f
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#define PAGE_LO_MASK 0x3ff
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#define PAGE_SEL_OFFSET_SHIFT 10
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#define PAB_CTRL 0x0808
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#define AMBA_PIO_ENABLE_SHIFT 0
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#define PEX_PIO_ENABLE_SHIFT 1
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#define PAGE_SEL_SHIFT 13
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#define PAGE_SEL_MASK 0x3f
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#define PAGE_LO_MASK 0x3ff
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#define PAGE_SEL_OFFSET_SHIFT 10
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#define PAB_AXI_PIO_CTRL 0x0840
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#define APIO_EN_MASK 0xf
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#define PAB_AXI_PIO_CTRL 0x0840
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#define APIO_EN_MASK 0xf
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#define PAB_PEX_PIO_CTRL 0x08c0
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#define PIO_ENABLE_SHIFT 0
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#define PAB_PEX_PIO_CTRL 0x08c0
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#define PIO_ENABLE_SHIFT 0
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#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
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#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
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#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
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#define PAB_INTP_INTX_MASK 0x01e0
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#define PAB_INTP_MSI_MASK 0x8
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#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
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#define WIN_ENABLE_SHIFT 0
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#define WIN_TYPE_SHIFT 1
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#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
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#define WIN_ENABLE_SHIFT 0
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#define WIN_TYPE_SHIFT 1
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#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
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@ -70,16 +72,16 @@
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#define AXI_WINDOW_ALIGN_MASK 3
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#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
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#define PAB_BUS_SHIFT 24
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#define PAB_DEVICE_SHIFT 19
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#define PAB_FUNCTION_SHIFT 16
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#define PAB_BUS_SHIFT 24
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#define PAB_DEVICE_SHIFT 19
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#define PAB_FUNCTION_SHIFT 16
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#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
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#define PAB_INTP_AXI_PIO_CLASS 0x474
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#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
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#define AMAP_CTRL_EN_SHIFT 0
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#define AMAP_CTRL_TYPE_SHIFT 1
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#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
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#define AMAP_CTRL_EN_SHIFT 0
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#define AMAP_CTRL_TYPE_SHIFT 1
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#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
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#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
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@ -87,39 +89,39 @@
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#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
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/* starting offset of INTX bits in status register */
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#define PAB_INTX_START 5
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#define PAB_INTX_START 5
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/* supported number of MSI interrupts */
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#define PCI_NUM_MSI 16
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#define PCI_NUM_MSI 16
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/* MSI registers */
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#define MSI_BASE_LO_OFFSET 0x04
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#define MSI_BASE_HI_OFFSET 0x08
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#define MSI_SIZE_OFFSET 0x0c
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#define MSI_ENABLE_OFFSET 0x14
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#define MSI_STATUS_OFFSET 0x18
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#define MSI_DATA_OFFSET 0x20
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#define MSI_ADDR_L_OFFSET 0x24
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#define MSI_ADDR_H_OFFSET 0x28
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#define MSI_BASE_LO_OFFSET 0x04
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#define MSI_BASE_HI_OFFSET 0x08
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#define MSI_SIZE_OFFSET 0x0c
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#define MSI_ENABLE_OFFSET 0x14
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#define MSI_STATUS_OFFSET 0x18
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#define MSI_DATA_OFFSET 0x20
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#define MSI_ADDR_L_OFFSET 0x24
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#define MSI_ADDR_H_OFFSET 0x28
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/* outbound and inbound window definitions */
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#define WIN_NUM_0 0
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#define WIN_NUM_1 1
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#define CFG_WINDOW_TYPE 0
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#define IO_WINDOW_TYPE 1
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#define MEM_WINDOW_TYPE 2
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#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
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#define MAX_PIO_WINDOWS 8
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#define WIN_NUM_0 0
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#define WIN_NUM_1 1
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#define CFG_WINDOW_TYPE 0
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#define IO_WINDOW_TYPE 1
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#define MEM_WINDOW_TYPE 2
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#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
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#define MAX_PIO_WINDOWS 8
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_MIN 90000
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#define LINK_WAIT_MAX 100000
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#define PAGED_ADDR_BNDRY 0xc00
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#define OFFSET_TO_PAGE_ADDR(off) \
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#define PAGED_ADDR_BNDRY 0xc00
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#define OFFSET_TO_PAGE_ADDR(off) \
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((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
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#define OFFSET_TO_PAGE_IDX(off) \
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#define OFFSET_TO_PAGE_IDX(off) \
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((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
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struct mobiveil_msi { /* MSI information */
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@ -294,17 +296,16 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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* root port or endpoint
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*/
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static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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unsigned int devfn, int where)
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{
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struct mobiveil_pcie *pcie = bus->sysdata;
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if (!mobiveil_pcie_valid_device(bus, devfn))
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return NULL;
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if (bus->number == pcie->root_bus_nr) {
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/* RC config access */
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/* RC config access */
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if (bus->number == pcie->root_bus_nr)
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return pcie->csr_axi_slave_base + where;
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}
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/*
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* EP config access (in Config/APIO space)
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@ -313,9 +314,9 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
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* Relies on pci_lock serialization
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*/
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csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
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PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
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PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
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PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
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return pcie->config_axi_slave_base + where;
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}
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@ -351,21 +352,21 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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/* Handle INTx */
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if (intr_status & PAB_INTP_INTX_MASK) {
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shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>
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PAB_INTX_START;
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PAB_INTX_START;
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do {
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for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
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virq = irq_find_mapping(pcie->intx_domain,
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bit + 1);
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bit + 1);
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if (virq)
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generic_handle_irq(virq);
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else
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dev_err_ratelimited(dev,
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"unexpected IRQ, INT%d\n", bit);
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dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
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bit);
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/* clear interrupt */
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csr_writel(pcie,
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shifted_status << PAB_INTX_START,
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PAB_INTP_AMBA_MISC_STAT);
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shifted_status << PAB_INTX_START,
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PAB_INTP_AMBA_MISC_STAT);
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}
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} while ((shifted_status >> PAB_INTX_START) != 0);
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}
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@ -375,8 +376,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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/* handle MSI interrupts */
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while (msi_status & 1) {
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msi_data = readl_relaxed(pcie->apb_csr_base
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+ MSI_DATA_OFFSET);
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msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
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/*
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* MSI_STATUS_OFFSET register gets updated to zero
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@ -385,18 +385,18 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
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* two dummy reads.
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*/
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msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_L_OFFSET);
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MSI_ADDR_L_OFFSET);
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msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
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MSI_ADDR_H_OFFSET);
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MSI_ADDR_H_OFFSET);
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dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
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msi_data, msi_addr_hi, msi_addr_lo);
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msi_data, msi_addr_hi, msi_addr_lo);
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virq = irq_find_mapping(msi->dev_domain, msi_data);
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if (virq)
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generic_handle_irq(virq);
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msi_status = readl_relaxed(pcie->apb_csr_base +
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MSI_STATUS_OFFSET);
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MSI_STATUS_OFFSET);
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}
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/* Clear the interrupt status */
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@ -413,7 +413,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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/* map config resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"config_axi_slave");
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"config_axi_slave");
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pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->config_axi_slave_base))
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return PTR_ERR(pcie->config_axi_slave_base);
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@ -421,7 +421,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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/* map csr resource */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"csr_axi_slave");
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"csr_axi_slave");
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pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(pcie->csr_axi_slave_base))
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return PTR_ERR(pcie->csr_axi_slave_base);
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@ -450,7 +450,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
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}
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static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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int pci_addr, u32 type, u64 size)
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int pci_addr, u32 type, u64 size)
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{
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int pio_ctrl_val;
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int amap_ctrl_dw;
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@ -463,8 +463,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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}
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pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
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csr_writel(pcie,
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pio_ctrl_val | (1 << PIO_ENABLE_SHIFT), PAB_PEX_PIO_CTRL);
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csr_writel(pcie, pio_ctrl_val | (1 << PIO_ENABLE_SHIFT),
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PAB_PEX_PIO_CTRL);
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amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
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amap_ctrl_dw = (amap_ctrl_dw | (type << AMAP_CTRL_TYPE_SHIFT));
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amap_ctrl_dw = (amap_ctrl_dw | (1 << AMAP_CTRL_EN_SHIFT));
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@ -484,7 +484,8 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
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* routine to program the outbound windows
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*/
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static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
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u64 cpu_addr, u64 pci_addr, u32 config_io_bit, u64 size)
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u64 cpu_addr, u64 pci_addr,
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u32 config_io_bit, u64 size)
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{
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u32 value, type;
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@ -503,7 +504,7 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
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type = config_io_bit;
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value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
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csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
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lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
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lower_32_bits(size64), PAB_AXI_AMAP_CTRL(win_num));
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csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
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@ -513,14 +514,14 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
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*/
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value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
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csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
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PAB_AXI_AMAP_AXI_WIN(win_num));
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PAB_AXI_AMAP_AXI_WIN(win_num));
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value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
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csr_writel(pcie, lower_32_bits(pci_addr),
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PAB_AXI_AMAP_PEX_WIN_L(win_num));
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PAB_AXI_AMAP_PEX_WIN_L(win_num));
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csr_writel(pcie, upper_32_bits(pci_addr),
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PAB_AXI_AMAP_PEX_WIN_H(win_num));
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PAB_AXI_AMAP_PEX_WIN_H(win_num));
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pcie->ob_wins_configured++;
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}
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@ -536,7 +537,9 @@ static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
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usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
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}
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dev_err(&pcie->pdev->dev, "link never came up\n");
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return -ETIMEDOUT;
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}
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@ -549,9 +552,9 @@ static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
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msi->msi_pages_phys = (phys_addr_t)msg_addr;
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writel_relaxed(lower_32_bits(msg_addr),
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pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
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pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
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writel_relaxed(upper_32_bits(msg_addr),
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pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
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pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
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writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
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writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
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}
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@ -573,7 +576,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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*/
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value = csr_readl(pcie, PCI_COMMAND);
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csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER, PCI_COMMAND);
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PCI_COMMAND_MASTER, PCI_COMMAND);
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/*
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* program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
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@ -581,10 +584,10 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
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*/
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pab_ctrl = csr_readl(pcie, PAB_CTRL);
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csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |
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(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
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(1 << PEX_PIO_ENABLE_SHIFT), PAB_CTRL);
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csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
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PAB_INTP_AMBA_MISC_ENB);
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PAB_INTP_AMBA_MISC_ENB);
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/*
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* program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
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@ -675,10 +678,11 @@ static struct irq_chip intx_irq_chip = {
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/* routine to setup the INTx related data */
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static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -713,7 +717,7 @@ static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
|||
}
|
||||
|
||||
static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
|
||||
const struct cpumask *mask, bool force)
|
||||
const struct cpumask *mask, bool force)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -725,7 +729,8 @@ static struct irq_chip mobiveil_msi_bottom_irq_chip = {
|
|||
};
|
||||
|
||||
static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs, void *args)
|
||||
unsigned int virq,
|
||||
unsigned int nr_irqs, void *args)
|
||||
{
|
||||
struct mobiveil_pcie *pcie = domain->host_data;
|
||||
struct mobiveil_msi *msi = &pcie->msi;
|
||||
|
|
@ -745,13 +750,13 @@ static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
|
|||
mutex_unlock(&msi->lock);
|
||||
|
||||
irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
|
||||
domain->host_data, handle_level_irq,
|
||||
NULL, NULL);
|
||||
domain->host_data, handle_level_irq, NULL, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs)
|
||||
unsigned int virq,
|
||||
unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
||||
struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
|
||||
|
|
@ -759,12 +764,11 @@ static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
|
|||
|
||||
mutex_lock(&msi->lock);
|
||||
|
||||
if (!test_bit(d->hwirq, msi->msi_irq_in_use)) {
|
||||
if (!test_bit(d->hwirq, msi->msi_irq_in_use))
|
||||
dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
|
||||
d->hwirq);
|
||||
} else {
|
||||
else
|
||||
__clear_bit(d->hwirq, msi->msi_irq_in_use);
|
||||
}
|
||||
|
||||
mutex_unlock(&msi->lock);
|
||||
}
|
||||
|
|
@ -788,12 +792,14 @@ static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
|
|||
}
|
||||
|
||||
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
|
||||
&mobiveil_msi_domain_info, msi->dev_domain);
|
||||
&mobiveil_msi_domain_info,
|
||||
msi->dev_domain);
|
||||
if (!msi->msi_domain) {
|
||||
dev_err(dev, "failed to create MSI domain\n");
|
||||
irq_domain_remove(msi->dev_domain);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -804,8 +810,8 @@ static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
|
|||
int ret;
|
||||
|
||||
/* setup INTx */
|
||||
pcie->intx_domain = irq_domain_add_linear(node,
|
||||
PCI_NUM_INTX, &intx_domain_ops, pcie);
|
||||
pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
|
||||
&intx_domain_ops, pcie);
|
||||
|
||||
if (!pcie->intx_domain) {
|
||||
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||||
|
|
@ -925,10 +931,10 @@ MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
|
|||
static struct platform_driver mobiveil_pcie_driver = {
|
||||
.probe = mobiveil_pcie_probe,
|
||||
.driver = {
|
||||
.name = "mobiveil-pcie",
|
||||
.of_match_table = mobiveil_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.name = "mobiveil-pcie",
|
||||
.of_match_table = mobiveil_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(mobiveil_pcie_driver);
|
||||
|
|
|
|||
Loading…
Reference in New Issue