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@ -59,8 +59,6 @@
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struct spi_imx_config {
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unsigned int speed_hz;
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unsigned int bpw;
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unsigned int mode;
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u8 cs;
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};
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enum spi_imx_devtype {
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@ -76,7 +74,7 @@ struct spi_imx_data;
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struct spi_imx_devtype_data {
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void (*intctrl)(struct spi_imx_data *, int);
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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int (*config)(struct spi_device *, struct spi_imx_config *);
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void (*trigger)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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void (*reset)(struct spi_imx_data *);
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@ -112,7 +110,6 @@ struct spi_imx_data {
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struct completion dma_tx_completion;
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const struct spi_imx_devtype_data *devtype_data;
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int chipselect[0];
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};
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static inline int is_imx27_cspi(struct spi_imx_data *d)
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@ -312,7 +309,7 @@ static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
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(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
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}
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static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
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static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned val = 0;
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@ -325,7 +322,7 @@ static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int
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writel(val, spi_imx->base + MX51_ECSPI_INT);
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}
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static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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{
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u32 reg;
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@ -334,9 +331,10 @@ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
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}
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static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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static int mx51_ecspi_config(struct spi_device *spi,
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struct spi_imx_config *config)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
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u32 clk = config->speed_hz, delay, reg;
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u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
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@ -355,28 +353,28 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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spi_imx->spi_bus_clk = clk;
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/* set chip select to use */
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ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
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ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
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ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
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cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
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cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
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if (config->mode & SPI_CPHA)
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cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
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if (spi->mode & SPI_CPHA)
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cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
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else
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cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
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cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
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if (config->mode & SPI_CPOL) {
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cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
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cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
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if (spi->mode & SPI_CPOL) {
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cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
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cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
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} else {
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cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
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cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
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cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
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cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
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}
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if (config->mode & SPI_CS_HIGH)
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cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
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if (spi->mode & SPI_CS_HIGH)
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cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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else
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cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
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cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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if (spi_imx->usedma)
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ctrl |= MX51_ECSPI_CTRL_SMC;
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@ -385,7 +383,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
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if (config->mode & SPI_LOOP)
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if (spi->mode & SPI_LOOP)
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reg |= MX51_ECSPI_TESTREG_LBC;
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else
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reg &= ~MX51_ECSPI_TESTREG_LBC;
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@ -424,12 +422,12 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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return 0;
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}
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static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
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static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
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}
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static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
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static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
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{
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/* drain receive buffer */
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while (mx51_ecspi_rx_available(spi_imx))
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@ -459,7 +457,7 @@ static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
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* the i.MX35 has a slightly different register layout for bits
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* we do not use here.
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*/
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static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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@ -471,7 +469,7 @@ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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static void mx31_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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@ -480,11 +478,10 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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static int mx31_config(struct spi_device *spi, struct spi_imx_config *config)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX31_CSPICTRL_DR_SHIFT;
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|
@ -496,14 +493,14 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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}
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if (config->mode & SPI_CPHA)
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if (spi->mode & SPI_CPHA)
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reg |= MX31_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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if (spi->mode & SPI_CPOL)
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reg |= MX31_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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if (spi->mode & SPI_CS_HIGH)
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reg |= MX31_CSPICTRL_SSPOL;
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if (cs < 0)
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reg |= (cs + 32) <<
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if (spi->cs_gpio < 0)
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reg |= (spi->cs_gpio + 32) <<
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|
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(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
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MX31_CSPICTRL_CS_SHIFT);
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|
@ -512,12 +509,12 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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return 0;
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}
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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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static int mx31_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}
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static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
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static void mx31_reset(struct spi_imx_data *spi_imx)
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{
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/* drain receive buffer */
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while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
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|
@ -537,7 +534,7 @@ static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
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#define MX21_CSPICTRL_DR_SHIFT 14
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#define MX21_CSPICTRL_CS_SHIFT 19
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static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
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static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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@ -549,7 +546,7 @@ static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
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static void mx21_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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@ -558,37 +555,36 @@ static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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|
|
static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
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|
|
struct spi_imx_config *config)
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|
|
static int mx21_config(struct spi_device *spi, struct spi_imx_config *config)
|
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|
|
{
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|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
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|
|
|
unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
|
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|
|
|
int cs = spi_imx->chipselect[config->cs];
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|
|
|
unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
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|
|
reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
|
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|
|
|
MX21_CSPICTRL_DR_SHIFT;
|
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|
|
reg |= config->bpw - 1;
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|
|
if (config->mode & SPI_CPHA)
|
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
|
reg |= MX21_CSPICTRL_PHA;
|
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|
|
|
if (config->mode & SPI_CPOL)
|
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
|
reg |= MX21_CSPICTRL_POL;
|
|
|
|
|
if (config->mode & SPI_CS_HIGH)
|
|
|
|
|
if (spi->mode & SPI_CS_HIGH)
|
|
|
|
|
reg |= MX21_CSPICTRL_SSPOL;
|
|
|
|
|
if (cs < 0)
|
|
|
|
|
reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
|
|
|
|
|
if (spi->cs_gpio < 0)
|
|
|
|
|
reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT;
|
|
|
|
|
|
|
|
|
|
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
|
|
|
|
|
static int mx21_rx_available(struct spi_imx_data *spi_imx)
|
|
|
|
|
{
|
|
|
|
|
return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
|
|
|
|
|
static void mx21_reset(struct spi_imx_data *spi_imx)
|
|
|
|
|
{
|
|
|
|
|
writel(1, spi_imx->base + MXC_RESET);
|
|
|
|
|
}
|
|
|
|
@ -604,7 +600,7 @@ static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
|
|
|
|
|
#define MX1_CSPICTRL_MASTER (1 << 10)
|
|
|
|
|
#define MX1_CSPICTRL_DR_SHIFT 13
|
|
|
|
|
|
|
|
|
|
static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|
|
|
|
static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|
|
|
|
{
|
|
|
|
|
unsigned int val = 0;
|
|
|
|
|
|
|
|
|
@ -616,7 +612,7 @@ static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|
|
|
|
writel(val, spi_imx->base + MXC_CSPIINT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
|
|
|
|
|
static void mx1_trigger(struct spi_imx_data *spi_imx)
|
|
|
|
|
{
|
|
|
|
|
unsigned int reg;
|
|
|
|
|
|
|
|
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@ -625,18 +621,18 @@ static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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static int mx1_config(struct spi_device *spi, struct spi_imx_config *config)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX1_CSPICTRL_DR_SHIFT;
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reg |= config->bpw - 1;
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if (config->mode & SPI_CPHA)
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if (spi->mode & SPI_CPHA)
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reg |= MX1_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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if (spi->mode & SPI_CPOL)
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reg |= MX1_CSPICTRL_POL;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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@ -644,12 +640,12 @@ static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
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return 0;
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}
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static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
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static int mx1_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
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}
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static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
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static void mx1_reset(struct spi_imx_data *spi_imx)
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{
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writel(1, spi_imx->base + MXC_RESET);
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}
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@ -747,15 +743,13 @@ MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
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static void spi_imx_chipselect(struct spi_device *spi, int is_active)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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int gpio = spi_imx->chipselect[spi->chip_select];
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int active = is_active != BITBANG_CS_INACTIVE;
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int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
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if (!gpio_is_valid(gpio))
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if (!gpio_is_valid(spi->cs_gpio))
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return;
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gpio_set_value(gpio, dev_is_lowactive ^ active);
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gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
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}
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static void spi_imx_push(struct spi_imx_data *spi_imx)
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@ -859,8 +853,6 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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config.bpw = t ? t->bits_per_word : spi->bits_per_word;
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config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
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config.mode = spi->mode;
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config.cs = spi->chip_select;
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if (!config.speed_hz)
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config.speed_hz = spi->max_speed_hz;
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@ -891,7 +883,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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return ret;
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}
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spi_imx->devtype_data->config(spi_imx, &config);
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spi_imx->devtype_data->config(spi, &config);
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return 0;
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}
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@ -1050,6 +1042,8 @@ static int spi_imx_pio_transfer(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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unsigned long transfer_timeout;
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unsigned long timeout;
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spi_imx->tx_buf = transfer->tx_buf;
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spi_imx->rx_buf = transfer->rx_buf;
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@ -1062,7 +1056,15 @@ static int spi_imx_pio_transfer(struct spi_device *spi,
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spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
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wait_for_completion(&spi_imx->xfer_done);
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transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
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timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
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transfer_timeout);
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if (!timeout) {
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dev_err(&spi->dev, "I/O Error in PIO\n");
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spi_imx->devtype_data->reset(spi_imx);
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return -ETIMEDOUT;
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}
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return transfer->len;
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}
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@ -1080,14 +1082,12 @@ static int spi_imx_transfer(struct spi_device *spi,
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static int spi_imx_setup(struct spi_device *spi)
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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int gpio = spi_imx->chipselect[spi->chip_select];
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dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
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spi->mode, spi->bits_per_word, spi->max_speed_hz);
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if (gpio_is_valid(gpio))
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gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
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if (gpio_is_valid(spi->cs_gpio))
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gpio_direction_output(spi->cs_gpio,
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spi->mode & SPI_CS_HIGH ? 0 : 1);
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spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
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@ -1137,31 +1137,21 @@ static int spi_imx_probe(struct platform_device *pdev)
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struct spi_master *master;
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struct spi_imx_data *spi_imx;
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struct resource *res;
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int i, ret, num_cs, irq;
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int i, ret, irq;
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if (!np && !mxc_platform_info) {
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dev_err(&pdev->dev, "can't get the platform data\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
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if (ret < 0) {
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if (mxc_platform_info)
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num_cs = mxc_platform_info->num_chipselect;
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else
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return ret;
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}
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master = spi_alloc_master(&pdev->dev,
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sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
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master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
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if (!master)
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return -ENOMEM;
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platform_set_drvdata(pdev, master);
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
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master->bus_num = pdev->id;
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master->num_chipselect = num_cs;
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master->bus_num = np ? -1 : pdev->id;
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spi_imx = spi_master_get_devdata(master);
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spi_imx->bitbang.master = master;
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@ -1170,22 +1160,16 @@ static int spi_imx_probe(struct platform_device *pdev)
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spi_imx->devtype_data = of_id ? of_id->data :
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(struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
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for (i = 0; i < master->num_chipselect; i++) {
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int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
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if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
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cs_gpio = mxc_platform_info->chipselect[i];
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if (mxc_platform_info) {
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master->num_chipselect = mxc_platform_info->num_chipselect;
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master->cs_gpios = devm_kzalloc(&master->dev,
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sizeof(int) * master->num_chipselect, GFP_KERNEL);
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if (!master->cs_gpios)
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return -ENOMEM;
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spi_imx->chipselect[i] = cs_gpio;
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if (!gpio_is_valid(cs_gpio))
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continue;
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ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
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DRIVER_NAME);
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if (ret) {
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dev_err(&pdev->dev, "can't get cs gpios\n");
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goto out_master_put;
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}
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}
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for (i = 0; i < master->num_chipselect; i++)
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master->cs_gpios[i] = mxc_platform_info->chipselect[i];
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}
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spi_imx->bitbang.chipselect = spi_imx_chipselect;
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spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
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@ -1267,6 +1251,19 @@ static int spi_imx_probe(struct platform_device *pdev)
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goto out_clk_put;
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}
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for (i = 0; i < master->num_chipselect; i++) {
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if (!gpio_is_valid(master->cs_gpios[i]))
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continue;
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ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
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DRIVER_NAME);
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if (ret) {
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dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
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master->cs_gpios[i]);
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goto out_clk_put;
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}
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}
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dev_info(&pdev->dev, "probed\n");
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clk_disable(spi_imx->clk_ipg);
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