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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (41 commits)
  m68knommu: external interrupt support to ColdFire intc-simr controller
  m68knommu: external interrupt support to ColdFire intc-2 controller
  m68knommu: remove ColdFire CLOCK_DIV config option
  m68knommu: fix gpio warnings for ColdFire 5407 targets
  m68knommu: fix gpio warnings for ColdFire 532x targets
  m68knommu: fix gpio warnings for ColdFire 5307 targets
  m68knommu: fix gpio warnings for ColdFire 527x targets
  m68knommu: fix gpio warnings for ColdFire 5272 targets
  m68knommu: fix gpio warnings for ColdFire 5249 targets
  m68knommu: fix gpio warnings for ColdFire 523x targets
  m68knommu: fix gpio warnings for ColdFire 520x targets
  m68knommu: fix gpio warnings for ColdFire 5206e targets
  m68knommu: fix gpio warnings for ColdFire 5206 targets
  m68knommu: fixing compiler warnings
  m68knommu: limit interrupts supported by ColdFire intc-simr driver
  m68knommu: move some init code out of unmask routine for ColdFire intc-2
  m68knommu: limit interrupts supported by ColdFire intc-2 driver
  m68knommu: add basic support for the ColdFire based FireBee board
  m68knommu: make ColdFire internal peripheral region configurable
  m68knommu: clean up definitions of ColdFire peripheral base registers
  ...
This commit is contained in:
Linus Torvalds 2011-03-16 19:02:36 -07:00
parent 242e5d06be 47e0c7e128
commit e34551339a
45 changed files with 1287 additions and 838 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
arch/m68k/include/asm/coldfire.h
View File

@ -14,39 +14,35 @@
/*
* Define master clock frequency. This is essentially done at config
* time now. No point enumerating dozens of possible clock options
* here. Also the peripheral clock (bus clock) divide ratio is set
* at config time too.
* Define master clock frequency. This is done at config time now.
* No point enumerating dozens of possible clock options here. And
* in any case new boards come along from time to time that have yet
* another different clocking frequency.
*/
#ifdef CONFIG_CLOCK_SET
#define MCF_CLK CONFIG_CLOCK_FREQ
#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
#else
#error "Don't know what your ColdFire CPU clock frequency is??"
#endif
/*
* Define the processor support peripherals base address.
* This is generally setup by the boards start up code.
* Define the processor internal peripherals base address.
*
* The majority of ColdFire parts use an MBAR register to set
* the base address. Some have an IPSBAR register instead, and it
* has slightly different rules on its size and alignment. Some
* parts have fixed addresses and the internal peripherals cannot
* be relocated in the CPU address space.
*
* The value of MBAR or IPSBAR is config time selectable, we no
* longer hard define it here. No MBAR or IPSBAR will be defined if
* this part has a fixed peripheral address map.
*/
#define MCF_MBAR 0x10000000
#define MCF_MBAR2 0x80000000
#if defined(CONFIG_M54xx)
#define MCF_IPSBAR MCF_MBAR
#elif defined(CONFIG_M520x)
#define MCF_IPSBAR 0xFC000000
#else
#define MCF_IPSBAR 0x40000000
#ifdef CONFIG_MBAR
#define MCF_MBAR CONFIG_MBAR
#endif
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x)
#undef MCF_MBAR
#define MCF_MBAR MCF_IPSBAR
#elif defined(CONFIG_M532x)
#undef MCF_MBAR
#define MCF_MBAR 0x00000000
#ifdef CONFIG_IPSBAR
#define MCF_IPSBAR CONFIG_IPSBAR
#endif
/****************************************************************************/

23
arch/m68k/include/asm/m5206sim.h
View File

@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
@ -48,14 +49,14 @@
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
@ -89,9 +90,15 @@
#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
#endif
#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */

50
arch/m68k/include/asm/m520xsim.h
View File

@ -13,13 +13,14 @@
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@ -35,9 +36,9 @@
* address to the SIMR and CIMR registers (not offsets into IPSBAR).
* The 520x family only has a single INTC unit.
*/
#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC1_SIMR (0)
#define MCFINTC1_CIMR (0)
#define MCFINTC1_ICR0 (0)
@ -52,19 +53,22 @@
/*
* SDRAM configuration registers.
*/
#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
#define MCFEPORT_EPPAR 0xFC088000
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPIER 0xFC088003
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005
#define MCFEPORT_EPFR 0xFC088006
#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
#define MCFGPIO_PODR_BE 0xFC0A4001
@ -119,10 +123,10 @@
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCF_GPIO_PAR_UART (0xA4036)
#define MCF_GPIO_PAR_FECI2C (0xA4033)
#define MCF_GPIO_PAR_QSPI (0xA4034)
#define MCF_GPIO_PAR_FEC (0xA4038)
#define MCF_GPIO_PAR_UART 0xFC0A4036
#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
#define MCF_GPIO_PAR_QSPI 0xFC0A4034
#define MCF_GPIO_PAR_FEC 0xFC0A4038
#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
@ -133,12 +137,24 @@
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
/*
* PIT timer module.
*/
#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
/*
* UART module.
*/
#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
/*
* FEC module.
*/
#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
#define MCFFEC_SIZE 0x800 /* Register set size */
/*
* Reset Controll Unit.

52
arch/m68k/include/asm/m523xsim.h
View File

@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 523x SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@ -39,11 +41,11 @@
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
* Reset Controll Unit (relative to IPSBAR).
@ -57,10 +59,19 @@
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
#define MCFFEC_SIZE 0x800
/*
* GPIO module.
*/
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
@ -117,13 +128,23 @@
#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/*
* EPort
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* Generic GPIO support
@ -143,5 +164,14 @@
*/
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
/****************************************************************************/
#endif /* m523xsim_h */

30
arch/m68k/include/asm/m5249sim.h
View File

@ -13,9 +13,15 @@
#define CPU_NAME "COLDFIRE(m5249)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* The 5249 has a second MBAR region, define its address.
*/
#define MCF_MBAR2 0x80000000
/*
* Define the 5249 SIM register set addresses.
*/
@ -55,11 +61,17 @@
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
/*
* UART module.
@ -67,6 +79,14 @@
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* Some symbol defines for the above...
*/

8
arch/m68k/include/asm/m5272sim.h
View File

@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
@ -80,6 +81,13 @@
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
/*
* Define system peripheral IRQ usage.
*/

68
arch/m68k/include/asm/m527xsim.h
View File

@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@ -42,29 +44,45 @@
* SDRAM configuration registers.
*/
#ifdef CONFIG_M5271
#define MCFSIM_DCR 0x40 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
#endif
#ifdef CONFIG_M5275
#define MCFSIM_DMR 0x40 /* SDRAM mode */
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
#endif
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
#define MCFFEC_SIZE0 0x800
#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
#define MCFFEC_SIZE1 0x800
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
@ -230,15 +248,23 @@
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
#endif
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/*
* EPort
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* GPIO pins setups to enable the UARTs.

44
arch/m68k/include/asm/m528xsim.h
View File

@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@ -39,18 +41,32 @@
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
/*
* UART module.
*/
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
#define MCFFEC_SIZE 0x800
/*
* GPIO registers
@ -162,6 +178,14 @@
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
/*
* Edge Port registers
*/

25
arch/m68k/include/asm/m5307sim.h
View File

@ -16,6 +16,7 @@
#define CPU_NAME "COLDFIRE(m5307)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m53xxacr.h>
@ -89,15 +90,29 @@
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#endif /* CONFIG_OLDMASK */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* UART module.
*/

9
arch/m68k/include/asm/m532xsim.h
View File

@ -11,6 +11,7 @@
#define CPU_NAME "COLDFIRE(m532x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 3)
#include <asm/m53xxacr.h>
@ -85,6 +86,14 @@
#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
/*********************************************************************
*
* Reset Controller Module

25
arch/m68k/include/asm/m5407sim.h
View File

@ -16,6 +16,7 @@
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
@ -72,11 +73,17 @@
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
@ -84,6 +91,14 @@
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* Generic GPIO support
*/

14
arch/m68k/include/asm/m54xxsim.h
View File

@ -7,6 +7,7 @@
#define CPU_NAME "COLDFIRE(m54xx)"
#define CPU_INSTR_PER_JIFFY 2
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
@ -15,7 +16,8 @@
/*
* Interrupt Controller Registers
*/
#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@ -47,6 +49,16 @@
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/*
* EDGE Port support.
*/
#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
/*
* Some PSC related definitions
*/

23
arch/m68k/include/asm/mcfdma.h
View File

@ -11,29 +11,6 @@
#define mcfdma_h
/****************************************************************************/
/*
* Get address specific defines for this Coldfire member.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
#elif defined(CONFIG_M5272)
#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
/* These are relative to the IPSBAR, not MBAR */
#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
#endif
#if !defined(CONFIG_M5272)
/*

16
arch/m68k/include/asm/mcfpit.h
View File

@ -11,22 +11,8 @@
#define mcfpit_h
/****************************************************************************/
/*
* Get address specific defines for the 5270/5271, 5280/5282, and 5208.
*/
#if defined(CONFIG_M520x)
#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
#else
#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
#endif
/*
* Define the PIT timer register set addresses.
* Define the PIT timer register address offsets.
*/
#define MCFPIT_PCSR 0x0 /* PIT control register */
#define MCFPIT_PMR 0x2 /* PIT modulus register */

23
arch/m68k/include/asm/mcftimer.h
View File

@ -12,29 +12,6 @@
#define mcftimer_h
/****************************************************************************/
/*
* Get address specific defines for this ColdFire member.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
#elif defined(CONFIG_M5272)
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
#elif defined(CONFIG_M532x)
#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
#endif
/*
* Define the TIMER register set addresses.
*/

58
arch/m68knommu/Kconfig
View File

@ -3,6 +3,7 @@ config M68K
default y
select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
config MMU
bool
@ -78,6 +79,12 @@ config HAVE_CACHE_SPLIT
config HAVE_CACHE_CB
bool
config HAVE_MBAR
bool
config HAVE_IPSBAR
bool
source "init/Kconfig"
source "kernel/Kconfig.freezer"
@ -111,12 +118,14 @@ config M68360
config M5206
bool "MCF5206"
select COLDFIRE_SW_A7
select HAVE_MBAR
help
Motorola ColdFire 5206 processor support.
config M5206e
bool "MCF5206e"
select COLDFIRE_SW_A7
select HAVE_MBAR
help
Motorola ColdFire 5206e processor support.
@ -131,30 +140,35 @@ config M523x
bool "MCF523x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
Freescale Coldfire 5230/1/2/4/5 processor support
config M5249
bool "MCF5249"
select COLDFIRE_SW_A7
select HAVE_MBAR
help
Motorola ColdFire 5249 processor support.
config M5271
bool "MCF5271"
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
Freescale (Motorola) ColdFire 5270/5271 processor support.
config M5272
bool "MCF5272"
select COLDFIRE_SW_A7
select HAVE_MBAR
help
Motorola ColdFire 5272 processor support.
config M5275
bool "MCF5275"
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
Freescale (Motorola) ColdFire 5274/5275 processor support.
@ -162,6 +176,7 @@ config M528x
bool "MCF528x"
select GENERIC_CLOCKEVENTS
select HAVE_CACHE_SPLIT
select HAVE_IPSBAR
help
Motorola ColdFire 5280/5282 processor support.
@ -169,6 +184,7 @@ config M5307
bool "MCF5307"
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
select HAVE_MBAR
help
Motorola ColdFire 5307 processor support.
@ -182,18 +198,21 @@ config M5407
bool "MCF5407"
select COLDFIRE_SW_A7
select HAVE_CACHE_CB
select HAVE_MBAR
help
Motorola ColdFire 5407 processor support.
config M547x
bool "MCF547x"
select HAVE_CACHE_CB
select HAVE_MBAR
help
Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
config M548x
bool "MCF548x"
select HAVE_CACHE_CB
select HAVE_MBAR
help
Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
@ -241,17 +260,6 @@ config CLOCK_FREQ
if it is fitted (there are some exceptions). This value will be
specific to the exact CPU that you are using.
config CLOCK_DIV
int "Set the core/bus clock divide ratio"
default "1"
depends on CLOCK_SET
help
On many SoC style CPUs the master CPU clock is also used to drive
on-chip peripherals. The clock that is distributed to these
peripherals is sometimes a fixed ratio of the master clock
frequency. If so then set this to the divider ratio of the
master clock to the peripheral clock. If not sure then select 1.
config OLDMASK
bool "Old mask 5307 (1H55J) silicon"
depends on M5307
@ -500,6 +508,12 @@ config M5407C3
help
Support for the Motorola M5407C3 board.
config FIREBEE
bool "FireBee board support"
depends on M547x
help
Support for the FireBee ColdFire 5475 based board.
config CLEOPATRA
bool "Feith CLEOPATRA board support"
depends on (M5307 || M5407)
@ -649,6 +663,28 @@ config VECTORBASE
platforms this address is programmed into the VBR register, thus
actually setting the address to use.
config MBAR
hex "Address of the MBAR (internal peripherals)"
default "0x10000000"
depends on HAVE_MBAR
help
Define the address of the internal system peripherals. This value
is set in the processors MBAR register. This is generally setup by
the boot loader, and will not be written by the kernel. By far most
ColdFire boards use the default 0x10000000 value, so if unsure then
use this.
config IPSBAR
hex "Address of the IPSBAR (internal peripherals)"
default "0x40000000"
depends on HAVE_IPSBAR
help
Define the address of the internal system peripherals. This value
is set in the processors IPSBAR register. This is generally setup by
the boot loader, and will not be written by the kernel. By far most
ColdFire boards use the default 0x40000000 value, so if unsure then
use this.
config KERNELBASE
hex "Address of the base of kernel code"
default "0x400"

6
arch/m68knommu/kernel/irq.c
View File

@ -38,11 +38,13 @@ int show_interrupts(struct seq_file *p, void *v)
seq_puts(p, " CPU0\n");
if (irq < NR_IRQS) {
ap = irq_desc[irq].action;
struct irq_desc *desc = irq_to_desc(irq);
ap = desc->action;
if (ap) {
seq_printf(p, "%3d: ", irq);
seq_printf(p, "%10u ", kstat_irqs(irq));
seq_printf(p, "%14s ", irq_desc[irq].chip->name);
seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name);
seq_printf(p, "%s", ap->name);
for (ap = ap->next; ap; ap = ap->next)

6
arch/m68knommu/platform/5206/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 8,
},
.pddr = MCFSIM_PADDR,
.podr = MCFSIM_PADAT,
.ppdr = MCFSIM_PADAT,
.pddr = (void __iomem *) MCFSIM_PADDR,
.podr = (void __iomem *) MCFSIM_PADAT,
.ppdr = (void __iomem *) MCFSIM_PADAT,
},
};

6
arch/m68knommu/platform/5206e/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 8,
},
.pddr = MCFSIM_PADDR,
.podr = MCFSIM_PADAT,
.ppdr = MCFSIM_PADAT,
.pddr = (void __iomem *) MCFSIM_PADDR,
.podr = (void __iomem *) MCFSIM_PADAT,
.ppdr = (void __iomem *) MCFSIM_PADAT,
},
};

36
arch/m68knommu/platform/520x/config.c
View File

@ -27,15 +27,15 @@
static struct mcf_platform_uart m520x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.mapbase = MCFUART_BASE1,
.irq = MCFINT_VECBASE + MCFINT_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.mapbase = MCFUART_BASE2,
.irq = MCFINT_VECBASE + MCFINT_UART1,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.mapbase = MCFUART_BASE3,
.irq = MCFINT_VECBASE + MCFINT_UART2,
},
{ },
@ -49,8 +49,8 @@ static struct platform_device m520x_uart = {
static struct resource m520x_fec_resources[] = {
{
.start = MCF_MBAR + 0x30000,
.end = MCF_MBAR + 0x30000 + 0x7ff,
.start = MCFFEC_BASE,
.end = MCFFEC_BASE + MCFFEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
@ -208,11 +208,11 @@ static void __init m520x_qspi_init(void)
{
u16 par;
/* setup Port QS for QSPI with gpio CS control */
writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI);
writeb(0x3f, MCF_GPIO_PAR_QSPI);
/* make U1CTS and U2RTS gpio for cs_control */
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
par = readw(MCF_GPIO_PAR_UART);
par &= 0x00ff;
writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
writew(par, MCF_GPIO_PAR_UART);
}
#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
@ -234,23 +234,23 @@ static void __init m520x_uart_init_line(int line, int irq)
switch (line) {
case 0:
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
par = readw(MCF_GPIO_PAR_UART);
par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
MCF_GPIO_PAR_UART_PAR_URXD0;
writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
writew(par, MCF_GPIO_PAR_UART);
break;
case 1:
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
par = readw(MCF_GPIO_PAR_UART);
par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
MCF_GPIO_PAR_UART_PAR_URXD1;
writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
writew(par, MCF_GPIO_PAR_UART);
break;
case 2:
par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
par2 = readb(MCF_GPIO_PAR_FECI2C);
par2 &= ~0x0F;
par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
writeb(par2, MCF_GPIO_PAR_FECI2C);
break;
}
}
@ -271,11 +271,11 @@ static void __init m520x_fec_init(void)
u8 v;
/* Set multi-function pins to ethernet mode */
v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
v = readb(MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
v = readb(MCF_GPIO_PAR_FECI2C);
writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
}
/***************************************************************************/

96
arch/m68knommu/platform/520x/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 8,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *) MCFEPORT_EPDDR,
.podr = (void __iomem *) MCFEPORT_EPDR,
.ppdr = (void __iomem *) MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 8,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BUSCTL,
.podr = MCFGPIO_PODR_BUSCTL,
.ppdr = MCFGPIO_PPDSDR_BUSCTL,
.setr = MCFGPIO_PPDSDR_BUSCTL,
.clrr = MCFGPIO_PCLRR_BUSCTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
.podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
},
{
.gpio_chip = {
@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BE,
.podr = MCFGPIO_PODR_BE,
.ppdr = MCFGPIO_PPDSDR_BE,
.setr = MCFGPIO_PPDSDR_BE,
.clrr = MCFGPIO_PCLRR_BE,
.pddr = (void __iomem *) MCFGPIO_PDDR_BE,
.podr = (void __iomem *) MCFGPIO_PODR_BE,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
},
{
.gpio_chip = {
@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 25,
.ngpio = 3,
},
.pddr = MCFGPIO_PDDR_CS,
.podr = MCFGPIO_PODR_CS,
.ppdr = MCFGPIO_PPDSDR_CS,
.setr = MCFGPIO_PPDSDR_CS,
.clrr = MCFGPIO_PCLRR_CS,
.pddr = (void __iomem *) MCFGPIO_PDDR_CS,
.podr = (void __iomem *) MCFGPIO_PODR_CS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
},
{
.gpio_chip = {
@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_FECI2C,
.podr = MCFGPIO_PODR_FECI2C,
.ppdr = MCFGPIO_PPDSDR_FECI2C,
.setr = MCFGPIO_PPDSDR_FECI2C,
.clrr = MCFGPIO_PCLRR_FECI2C,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
.podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
},
{
.gpio_chip = {
@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_QSPI,
.podr = MCFGPIO_PODR_QSPI,
.ppdr = MCFGPIO_PPDSDR_QSPI,
.setr = MCFGPIO_PPDSDR_QSPI,
.clrr = MCFGPIO_PCLRR_QSPI,
.pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
.podr = (void __iomem *) MCFGPIO_PODR_QSPI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
},
{
.gpio_chip = {
@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 48,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_TIMER,
.podr = MCFGPIO_PODR_TIMER,
.ppdr = MCFGPIO_PPDSDR_TIMER,
.setr = MCFGPIO_PPDSDR_TIMER,
.clrr = MCFGPIO_PCLRR_TIMER,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
.podr = (void __iomem *) MCFGPIO_PODR_TIMER,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
},
{
.gpio_chip = {
@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 56,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_UART,
.podr = MCFGPIO_PODR_UART,
.ppdr = MCFGPIO_PPDSDR_UART,
.setr = MCFGPIO_PPDSDR_UART,
.clrr = MCFGPIO_PCLRR_UART,
.pddr = (void __iomem *) MCFGPIO_PDDR_UART,
.podr = (void __iomem *) MCFGPIO_PODR_UART,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
},
{
.gpio_chip = {
@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FECH,
.podr = MCFGPIO_PODR_FECH,
.ppdr = MCFGPIO_PPDSDR_FECH,
.setr = MCFGPIO_PPDSDR_FECH,
.clrr = MCFGPIO_PCLRR_FECH,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
.podr = (void __iomem *) MCFGPIO_PODR_FECH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
},
{
.gpio_chip = {
@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FECL,
.podr = MCFGPIO_PODR_FECL,
.ppdr = MCFGPIO_PPDSDR_FECL,
.setr = MCFGPIO_PPDSDR_FECL,
.clrr = MCFGPIO_PCLRR_FECL,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
.podr = (void __iomem *) MCFGPIO_PODR_FECL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
},
};

10
arch/m68knommu/platform/523x/config.c
View File

@ -28,15 +28,15 @@
static struct mcf_platform_uart m523x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.mapbase = MCFUART_BASE1,
.irq = MCFINT_VECBASE + MCFINT_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.mapbase = MCFUART_BASE2,
.irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.mapbase = MCFUART_BASE3,
.irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
},
{ },
@ -50,8 +50,8 @@ static struct platform_device m523x_uart = {
static struct resource m523x_fec_resources[] = {
{
.start = MCF_MBAR + 0x1000,
.end = MCF_MBAR + 0x1000 + 0x7ff,
.start = MCFFEC_BASE,
.end = MCFFEC_BASE + MCFFEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{

136
arch/m68knommu/platform/523x/gpio.c
View File

@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 1,
.ngpio = 7,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *) MCFEPORT_EPDDR,
.podr = (void __iomem *) MCFEPORT_EPDR,
.ppdr = (void __iomem *) MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -49,11 +49,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 13,
.ngpio = 3,
},
.pddr = MCFGPIO_PDDR_ADDR,
.podr = MCFGPIO_PODR_ADDR,
.ppdr = MCFGPIO_PPDSDR_ADDR,
.setr = MCFGPIO_PPDSDR_ADDR,
.clrr = MCFGPIO_PCLRR_ADDR,
.pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
.podr = (void __iomem *) MCFGPIO_PODR_ADDR,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
},
{
.gpio_chip = {
@ -67,11 +67,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_DATAH,
.podr = MCFGPIO_PODR_DATAH,
.ppdr = MCFGPIO_PPDSDR_DATAH,
.setr = MCFGPIO_PPDSDR_DATAH,
.clrr = MCFGPIO_PCLRR_DATAH,
.pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
.podr = (void __iomem *) MCFGPIO_PODR_DATAH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
},
{
.gpio_chip = {
@ -85,11 +85,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 24,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_DATAL,
.podr = MCFGPIO_PODR_DATAL,
.ppdr = MCFGPIO_PPDSDR_DATAL,
.setr = MCFGPIO_PPDSDR_DATAL,
.clrr = MCFGPIO_PCLRR_DATAL,
.pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
.podr = (void __iomem *) MCFGPIO_PODR_DATAL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
},
{
.gpio_chip = {
@ -103,11 +103,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_BUSCTL,
.podr = MCFGPIO_PODR_BUSCTL,
.ppdr = MCFGPIO_PPDSDR_BUSCTL,
.setr = MCFGPIO_PPDSDR_BUSCTL,
.clrr = MCFGPIO_PCLRR_BUSCTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
.podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
},
{
.gpio_chip = {
@ -121,11 +121,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BS,
.podr = MCFGPIO_PODR_BS,
.ppdr = MCFGPIO_PPDSDR_BS,
.setr = MCFGPIO_PPDSDR_BS,
.clrr = MCFGPIO_PCLRR_BS,
.pddr = (void __iomem *) MCFGPIO_PDDR_BS,
.podr = (void __iomem *) MCFGPIO_PODR_BS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
},
{
.gpio_chip = {
@ -139,11 +139,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 49,
.ngpio = 7,
},
.pddr = MCFGPIO_PDDR_CS,
.podr = MCFGPIO_PODR_CS,
.ppdr = MCFGPIO_PPDSDR_CS,
.setr = MCFGPIO_PPDSDR_CS,
.clrr = MCFGPIO_PCLRR_CS,
.pddr = (void __iomem *) MCFGPIO_PDDR_CS,
.podr = (void __iomem *) MCFGPIO_PODR_CS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
},
{
.gpio_chip = {
@ -157,11 +157,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 56,
.ngpio = 6,
},
.pddr = MCFGPIO_PDDR_SDRAM,
.podr = MCFGPIO_PODR_SDRAM,
.ppdr = MCFGPIO_PPDSDR_SDRAM,
.setr = MCFGPIO_PPDSDR_SDRAM,
.clrr = MCFGPIO_PCLRR_SDRAM,
.pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
.podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
},
{
.gpio_chip = {
@ -175,11 +175,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_FECI2C,
.podr = MCFGPIO_PODR_FECI2C,
.ppdr = MCFGPIO_PPDSDR_FECI2C,
.setr = MCFGPIO_PPDSDR_FECI2C,
.clrr = MCFGPIO_PCLRR_FECI2C,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
.podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
},
{
.gpio_chip = {
@ -193,11 +193,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 2,
},
.pddr = MCFGPIO_PDDR_UARTH,
.podr = MCFGPIO_PODR_UARTH,
.ppdr = MCFGPIO_PPDSDR_UARTH,
.setr = MCFGPIO_PPDSDR_UARTH,
.clrr = MCFGPIO_PCLRR_UARTH,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
.podr = (void __iomem *) MCFGPIO_PODR_UARTH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
},
{
.gpio_chip = {
@ -211,11 +211,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 80,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_UARTL,
.podr = MCFGPIO_PODR_UARTL,
.ppdr = MCFGPIO_PPDSDR_UARTL,
.setr = MCFGPIO_PPDSDR_UARTL,
.clrr = MCFGPIO_PCLRR_UARTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
.podr = (void __iomem *) MCFGPIO_PODR_UARTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
},
{
.gpio_chip = {
@ -229,11 +229,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 88,
.ngpio = 5,
},
.pddr = MCFGPIO_PDDR_QSPI,
.podr = MCFGPIO_PODR_QSPI,
.ppdr = MCFGPIO_PPDSDR_QSPI,
.setr = MCFGPIO_PPDSDR_QSPI,
.clrr = MCFGPIO_PCLRR_QSPI,
.pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
.podr = (void __iomem *) MCFGPIO_PODR_QSPI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
},
{
.gpio_chip = {
@ -247,11 +247,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 96,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_TIMER,
.podr = MCFGPIO_PODR_TIMER,
.ppdr = MCFGPIO_PPDSDR_TIMER,
.setr = MCFGPIO_PPDSDR_TIMER,
.clrr = MCFGPIO_PCLRR_TIMER,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
.podr = (void __iomem *) MCFGPIO_PODR_TIMER,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
},
{
.gpio_chip = {
@ -265,11 +265,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 104,
.ngpio = 3,
},
.pddr = MCFGPIO_PDDR_ETPU,
.podr = MCFGPIO_PODR_ETPU,
.ppdr = MCFGPIO_PPDSDR_ETPU,
.setr = MCFGPIO_PPDSDR_ETPU,
.clrr = MCFGPIO_PCLRR_ETPU,
.pddr = (void __iomem *) MCFGPIO_PDDR_ETPU,
.podr = (void __iomem *) MCFGPIO_PODR_ETPU,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
.setr = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
.clrr = (void __iomem *) MCFGPIO_PCLRR_ETPU,
},
};

12
arch/m68knommu/platform/5249/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 32,
},
.pddr = MCFSIM2_GPIOENABLE,
.podr = MCFSIM2_GPIOWRITE,
.ppdr = MCFSIM2_GPIOREAD,
.pddr = (void __iomem *) MCFSIM2_GPIOENABLE,
.podr = (void __iomem *) MCFSIM2_GPIOWRITE,
.ppdr = (void __iomem *) MCFSIM2_GPIOREAD,
},
{
.gpio_chip = {
@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 32,
},
.pddr = MCFSIM2_GPIO1ENABLE,
.podr = MCFSIM2_GPIO1WRITE,
.ppdr = MCFSIM2_GPIO1READ,
.pddr = (void __iomem *) MCFSIM2_GPIO1ENABLE,
.podr = (void __iomem *) MCFSIM2_GPIO1WRITE,
.ppdr = (void __iomem *) MCFSIM2_GPIO1READ,
},
};

20
arch/m68knommu/platform/5249/intc2.c
View File

@ -17,32 +17,32 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
static void intc2_irq_gpio_mask(unsigned int irq)
static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr;
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0));
imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_unmask(unsigned int irq)
static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr;
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0));
imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(unsigned int irq)
static void intc2_irq_gpio_ack(struct irq_data *d)
{
writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
}
static struct irq_chip intc2_irq_gpio_chip = {
.name = "CF-INTC2",
.mask = intc2_irq_gpio_mask,
.unmask = intc2_irq_gpio_unmask,
.ack = intc2_irq_gpio_ack,
.irq_mask = intc2_irq_gpio_mask,
.irq_unmask = intc2_irq_gpio_unmask,
.irq_ack = intc2_irq_gpio_ack,
};
static int __init mcf_intc2_init(void)
@ -51,7 +51,7 @@ static int __init mcf_intc2_init(void)
/* GPIO interrupt sources */
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
irq_desc[irq].chip = &intc2_irq_gpio_chip;
set_irq_chip(irq, &intc2_irq_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
}

18
arch/m68knommu/platform/5272/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 16,
},
.pddr = MCFSIM_PADDR,
.podr = MCFSIM_PADAT,
.ppdr = MCFSIM_PADAT,
.pddr = (void __iomem *) MCFSIM_PADDR,
.podr = (void __iomem *) MCFSIM_PADAT,
.ppdr = (void __iomem *) MCFSIM_PADAT,
},
{
.gpio_chip = {
@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 16,
},
.pddr = MCFSIM_PBDDR,
.podr = MCFSIM_PBDAT,
.ppdr = MCFSIM_PBDAT,
.pddr = (void __iomem *) MCFSIM_PBDDR,
.podr = (void __iomem *) MCFSIM_PBDAT,
.ppdr = (void __iomem *) MCFSIM_PBDAT,
},
{
.gpio_chip = {
@ -64,9 +64,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 16,
},
.pddr = MCFSIM_PCDDR,
.podr = MCFSIM_PCDAT,
.ppdr = MCFSIM_PCDAT,
.pddr = (void __iomem *) MCFSIM_PCDDR,
.podr = (void __iomem *) MCFSIM_PCDAT,
.ppdr = (void __iomem *) MCFSIM_PCDAT,
},
};

33
arch/m68knommu/platform/5272/intc.c
View File

@ -78,8 +78,10 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
* an interrupt on this irq (for the external irqs). So this mask function
* is also an ack_mask function.
*/
static void intc_irq_mask(unsigned int irq)
static void intc_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
u32 v;
irq -= MCFINT_VECBASE;
@ -88,8 +90,10 @@ static void intc_irq_mask(unsigned int irq)
}
}
static void intc_irq_unmask(unsigned int irq)
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
u32 v;
irq -= MCFINT_VECBASE;
@ -98,8 +102,10 @@ static void intc_irq_unmask(unsigned int irq)
}
}
static void intc_irq_ack(unsigned int irq)
static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
/* Only external interrupts are acked */
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
irq -= MCFINT_VECBASE;
@ -113,8 +119,10 @@ static void intc_irq_ack(unsigned int irq)
}
}
static int intc_irq_set_type(unsigned int irq, unsigned int type)
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
@ -137,20 +145,17 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type)
*/
static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
{
kstat_incr_irqs_this_cpu(irq, desc);
desc->status |= IRQ_INPROGRESS;
desc->chip->ack(irq);
handle_IRQ_event(irq, desc->action);
desc->status &= ~IRQ_INPROGRESS;
get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
handle_simple_irq(irq, desc);
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.mask_ack = intc_irq_mask,
.ack = intc_irq_ack,
.set_type = intc_irq_set_type,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_mask_ack = intc_irq_mask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)

14
arch/m68knommu/platform/527x/config.c
View File

@ -28,15 +28,15 @@
static struct mcf_platform_uart m527x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.mapbase = MCFUART_BASE1,
.irq = MCFINT_VECBASE + MCFINT_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.mapbase = MCFUART_BASE2,
.irq = MCFINT_VECBASE + MCFINT_UART1,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.mapbase = MCFUART_BASE3,
.irq = MCFINT_VECBASE + MCFINT_UART2,
},
{ },
@ -50,8 +50,8 @@ static struct platform_device m527x_uart = {
static struct resource m527x_fec0_resources[] = {
{
.start = MCF_MBAR + 0x1000,
.end = MCF_MBAR + 0x1000 + 0x7ff,
.start = MCFFEC_BASE0,
.end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
@ -73,8 +73,8 @@ static struct resource m527x_fec0_resources[] = {
static struct resource m527x_fec1_resources[] = {
{
.start = MCF_MBAR + 0x1800,
.end = MCF_MBAR + 0x1800 + 0x7ff,
.start = MCFFEC_BASE1,
.end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
.flags = IORESOURCE_MEM,
},
{

312
arch/m68knommu/platform/527x/gpio.c
View File

@ -34,9 +34,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 1,
.ngpio = 7,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *) MCFEPORT_EPDDR,
.podr = (void __iomem *) MCFEPORT_EPDR,
.ppdr = (void __iomem *) MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -50,11 +50,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 13,
.ngpio = 3,
},
.pddr = MCFGPIO_PDDR_ADDR,
.podr = MCFGPIO_PODR_ADDR,
.ppdr = MCFGPIO_PPDSDR_ADDR,
.setr = MCFGPIO_PPDSDR_ADDR,
.clrr = MCFGPIO_PCLRR_ADDR,
.pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
.podr = (void __iomem *) MCFGPIO_PODR_ADDR,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
},
{
.gpio_chip = {
@ -68,11 +68,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_DATAH,
.podr = MCFGPIO_PODR_DATAH,
.ppdr = MCFGPIO_PPDSDR_DATAH,
.setr = MCFGPIO_PPDSDR_DATAH,
.clrr = MCFGPIO_PCLRR_DATAH,
.pddr = (void __iomem *) MCFGPIO_PDDR_DATAH,
.podr = (void __iomem *) MCFGPIO_PODR_DATAH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_DATAH,
},
{
.gpio_chip = {
@ -86,11 +86,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 24,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_DATAL,
.podr = MCFGPIO_PODR_DATAL,
.ppdr = MCFGPIO_PPDSDR_DATAL,
.setr = MCFGPIO_PPDSDR_DATAL,
.clrr = MCFGPIO_PCLRR_DATAL,
.pddr = (void __iomem *) MCFGPIO_PDDR_DATAL,
.podr = (void __iomem *) MCFGPIO_PODR_DATAL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_DATAL,
},
{
.gpio_chip = {
@ -104,11 +104,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_BUSCTL,
.podr = MCFGPIO_PODR_BUSCTL,
.ppdr = MCFGPIO_PPDSDR_BUSCTL,
.setr = MCFGPIO_PPDSDR_BUSCTL,
.clrr = MCFGPIO_PCLRR_BUSCTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
.podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
},
{
.gpio_chip = {
@ -122,11 +122,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BS,
.podr = MCFGPIO_PODR_BS,
.ppdr = MCFGPIO_PPDSDR_BS,
.setr = MCFGPIO_PPDSDR_BS,
.clrr = MCFGPIO_PCLRR_BS,
.pddr = (void __iomem *) MCFGPIO_PDDR_BS,
.podr = (void __iomem *) MCFGPIO_PODR_BS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
},
{
.gpio_chip = {
@ -140,11 +140,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 49,
.ngpio = 7,
},
.pddr = MCFGPIO_PDDR_CS,
.podr = MCFGPIO_PODR_CS,
.ppdr = MCFGPIO_PPDSDR_CS,
.setr = MCFGPIO_PPDSDR_CS,
.clrr = MCFGPIO_PCLRR_CS,
.pddr = (void __iomem *) MCFGPIO_PDDR_CS,
.podr = (void __iomem *) MCFGPIO_PODR_CS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
},
{
.gpio_chip = {
@ -158,11 +158,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 56,
.ngpio = 6,
},
.pddr = MCFGPIO_PDDR_SDRAM,
.podr = MCFGPIO_PODR_SDRAM,
.ppdr = MCFGPIO_PPDSDR_SDRAM,
.setr = MCFGPIO_PPDSDR_SDRAM,
.clrr = MCFGPIO_PCLRR_SDRAM,
.pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
.podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
},
{
.gpio_chip = {
@ -176,11 +176,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_FECI2C,
.podr = MCFGPIO_PODR_FECI2C,
.ppdr = MCFGPIO_PPDSDR_FECI2C,
.setr = MCFGPIO_PPDSDR_FECI2C,
.clrr = MCFGPIO_PCLRR_FECI2C,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
.podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
},
{
.gpio_chip = {
@ -194,11 +194,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 2,
},
.pddr = MCFGPIO_PDDR_UARTH,
.podr = MCFGPIO_PODR_UARTH,
.ppdr = MCFGPIO_PPDSDR_UARTH,
.setr = MCFGPIO_PPDSDR_UARTH,
.clrr = MCFGPIO_PCLRR_UARTH,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
.podr = (void __iomem *) MCFGPIO_PODR_UARTH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
},
{
.gpio_chip = {
@ -212,11 +212,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 80,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_UARTL,
.podr = MCFGPIO_PODR_UARTL,
.ppdr = MCFGPIO_PPDSDR_UARTL,
.setr = MCFGPIO_PPDSDR_UARTL,
.clrr = MCFGPIO_PCLRR_UARTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
.podr = (void __iomem *) MCFGPIO_PODR_UARTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
},
{
.gpio_chip = {
@ -230,11 +230,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 88,
.ngpio = 5,
},
.pddr = MCFGPIO_PDDR_QSPI,
.podr = MCFGPIO_PODR_QSPI,
.ppdr = MCFGPIO_PPDSDR_QSPI,
.setr = MCFGPIO_PPDSDR_QSPI,
.clrr = MCFGPIO_PCLRR_QSPI,
.pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
.podr = (void __iomem *) MCFGPIO_PODR_QSPI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
},
{
.gpio_chip = {
@ -248,11 +248,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 96,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_TIMER,
.podr = MCFGPIO_PODR_TIMER,
.ppdr = MCFGPIO_PPDSDR_TIMER,
.setr = MCFGPIO_PPDSDR_TIMER,
.clrr = MCFGPIO_PCLRR_TIMER,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
.podr = (void __iomem *) MCFGPIO_PODR_TIMER,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
},
#elif defined(CONFIG_M5275)
{
@ -267,9 +267,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 1,
.ngpio = 7,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *) MCFEPORT_EPDDR,
.podr = (void __iomem *) MCFEPORT_EPDR,
.ppdr = (void __iomem *) MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -283,11 +283,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 8,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_BUSCTL,
.podr = MCFGPIO_PODR_BUSCTL,
.ppdr = MCFGPIO_PPDSDR_BUSCTL,
.setr = MCFGPIO_PPDSDR_BUSCTL,
.clrr = MCFGPIO_PCLRR_BUSCTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
.podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
},
{
.gpio_chip = {
@ -301,11 +301,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 21,
.ngpio = 3,
},
.pddr = MCFGPIO_PDDR_ADDR,
.podr = MCFGPIO_PODR_ADDR,
.ppdr = MCFGPIO_PPDSDR_ADDR,
.setr = MCFGPIO_PPDSDR_ADDR,
.clrr = MCFGPIO_PCLRR_ADDR,
.pddr = (void __iomem *) MCFGPIO_PDDR_ADDR,
.podr = (void __iomem *) MCFGPIO_PODR_ADDR,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.setr = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
.clrr = (void __iomem *) MCFGPIO_PCLRR_ADDR,
},
{
.gpio_chip = {
@ -319,11 +319,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 25,
.ngpio = 7,
},
.pddr = MCFGPIO_PDDR_CS,
.podr = MCFGPIO_PODR_CS,
.ppdr = MCFGPIO_PPDSDR_CS,
.setr = MCFGPIO_PPDSDR_CS,
.clrr = MCFGPIO_PCLRR_CS,
.pddr = (void __iomem *) MCFGPIO_PDDR_CS,
.podr = (void __iomem *) MCFGPIO_PODR_CS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
},
{
.gpio_chip = {
@ -337,11 +337,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FEC0H,
.podr = MCFGPIO_PODR_FEC0H,
.ppdr = MCFGPIO_PPDSDR_FEC0H,
.setr = MCFGPIO_PPDSDR_FEC0H,
.clrr = MCFGPIO_PCLRR_FEC0H,
.pddr = (void __iomem *) MCFGPIO_PDDR_FEC0H,
.podr = (void __iomem *) MCFGPIO_PODR_FEC0H,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
},
{
.gpio_chip = {
@ -355,11 +355,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FEC0L,
.podr = MCFGPIO_PODR_FEC0L,
.ppdr = MCFGPIO_PPDSDR_FEC0L,
.setr = MCFGPIO_PPDSDR_FEC0L,
.clrr = MCFGPIO_PCLRR_FEC0L,
.pddr = (void __iomem *) MCFGPIO_PDDR_FEC0L,
.podr = (void __iomem *) MCFGPIO_PODR_FEC0L,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
},
{
.gpio_chip = {
@ -373,11 +373,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 48,
.ngpio = 6,
},
.pddr = MCFGPIO_PDDR_FECI2C,
.podr = MCFGPIO_PODR_FECI2C,
.ppdr = MCFGPIO_PPDSDR_FECI2C,
.setr = MCFGPIO_PPDSDR_FECI2C,
.clrr = MCFGPIO_PCLRR_FECI2C,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
.podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
},
{
.gpio_chip = {
@ -391,11 +391,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 56,
.ngpio = 7,
},
.pddr = MCFGPIO_PDDR_QSPI,
.podr = MCFGPIO_PODR_QSPI,
.ppdr = MCFGPIO_PPDSDR_QSPI,
.setr = MCFGPIO_PPDSDR_QSPI,
.clrr = MCFGPIO_PCLRR_QSPI,
.pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
.podr = (void __iomem *) MCFGPIO_PODR_QSPI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
},
{
.gpio_chip = {
@ -409,11 +409,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_SDRAM,
.podr = MCFGPIO_PODR_SDRAM,
.ppdr = MCFGPIO_PPDSDR_SDRAM,
.setr = MCFGPIO_PPDSDR_SDRAM,
.clrr = MCFGPIO_PCLRR_SDRAM,
.pddr = (void __iomem *) MCFGPIO_PDDR_SDRAM,
.podr = (void __iomem *) MCFGPIO_PODR_SDRAM,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.setr = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
.clrr = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
},
{
.gpio_chip = {
@ -427,11 +427,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_TIMERH,
.podr = MCFGPIO_PODR_TIMERH,
.ppdr = MCFGPIO_PPDSDR_TIMERH,
.setr = MCFGPIO_PPDSDR_TIMERH,
.clrr = MCFGPIO_PCLRR_TIMERH,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMERH,
.podr = (void __iomem *) MCFGPIO_PODR_TIMERH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
},
{
.gpio_chip = {
@ -445,11 +445,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 80,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_TIMERL,
.podr = MCFGPIO_PODR_TIMERL,
.ppdr = MCFGPIO_PPDSDR_TIMERL,
.setr = MCFGPIO_PPDSDR_TIMERL,
.clrr = MCFGPIO_PCLRR_TIMERL,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMERL,
.podr = (void __iomem *) MCFGPIO_PODR_TIMERL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
},
{
.gpio_chip = {
@ -463,11 +463,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 88,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_UARTL,
.podr = MCFGPIO_PODR_UARTL,
.ppdr = MCFGPIO_PPDSDR_UARTL,
.setr = MCFGPIO_PPDSDR_UARTL,
.clrr = MCFGPIO_PCLRR_UARTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTL,
.podr = (void __iomem *) MCFGPIO_PODR_UARTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTL,
},
{
.gpio_chip = {
@ -481,11 +481,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 96,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FEC1H,
.podr = MCFGPIO_PODR_FEC1H,
.ppdr = MCFGPIO_PPDSDR_FEC1H,
.setr = MCFGPIO_PPDSDR_FEC1H,
.clrr = MCFGPIO_PCLRR_FEC1H,
.pddr = (void __iomem *) MCFGPIO_PDDR_FEC1H,
.podr = (void __iomem *) MCFGPIO_PODR_FEC1H,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
},
{
.gpio_chip = {
@ -499,11 +499,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 104,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FEC1L,
.podr = MCFGPIO_PODR_FEC1L,
.ppdr = MCFGPIO_PPDSDR_FEC1L,
.setr = MCFGPIO_PPDSDR_FEC1L,
.clrr = MCFGPIO_PCLRR_FEC1L,
.pddr = (void __iomem *) MCFGPIO_PDDR_FEC1L,
.podr = (void __iomem *) MCFGPIO_PODR_FEC1L,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
},
{
.gpio_chip = {
@ -517,11 +517,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 114,
.ngpio = 2,
},
.pddr = MCFGPIO_PDDR_BS,
.podr = MCFGPIO_PODR_BS,
.ppdr = MCFGPIO_PPDSDR_BS,
.setr = MCFGPIO_PPDSDR_BS,
.clrr = MCFGPIO_PCLRR_BS,
.pddr = (void __iomem *) MCFGPIO_PDDR_BS,
.podr = (void __iomem *) MCFGPIO_PODR_BS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BS,
},
{
.gpio_chip = {
@ -535,11 +535,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 121,
.ngpio = 7,
},
.pddr = MCFGPIO_PDDR_IRQ,
.podr = MCFGPIO_PODR_IRQ,
.ppdr = MCFGPIO_PPDSDR_IRQ,
.setr = MCFGPIO_PPDSDR_IRQ,
.clrr = MCFGPIO_PCLRR_IRQ,
.pddr = (void __iomem *) MCFGPIO_PDDR_IRQ,
.podr = (void __iomem *) MCFGPIO_PODR_IRQ,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
.setr = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
.clrr = (void __iomem *) MCFGPIO_PCLRR_IRQ,
},
{
.gpio_chip = {
@ -553,11 +553,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 128,
.ngpio = 1,
},
.pddr = MCFGPIO_PDDR_USBH,
.podr = MCFGPIO_PODR_USBH,
.ppdr = MCFGPIO_PPDSDR_USBH,
.setr = MCFGPIO_PPDSDR_USBH,
.clrr = MCFGPIO_PCLRR_USBH,
.pddr = (void __iomem *) MCFGPIO_PDDR_USBH,
.podr = (void __iomem *) MCFGPIO_PODR_USBH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_USBH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_USBH,
},
{
.gpio_chip = {
@ -571,11 +571,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 136,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_USBL,
.podr = MCFGPIO_PODR_USBL,
.ppdr = MCFGPIO_PPDSDR_USBL,
.setr = MCFGPIO_PPDSDR_USBL,
.clrr = MCFGPIO_PCLRR_USBL,
.pddr = (void __iomem *) MCFGPIO_PDDR_USBL,
.podr = (void __iomem *) MCFGPIO_PODR_USBL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_USBL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_USBL,
},
{
.gpio_chip = {
@ -589,11 +589,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 144,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_UARTH,
.podr = MCFGPIO_PODR_UARTH,
.ppdr = MCFGPIO_PPDSDR_UARTH,
.setr = MCFGPIO_PPDSDR_UARTH,
.clrr = MCFGPIO_PCLRR_UARTH,
.pddr = (void __iomem *) MCFGPIO_PDDR_UARTH,
.podr = (void __iomem *) MCFGPIO_PODR_UARTH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UARTH,
},
#endif
};

14
arch/m68knommu/platform/528x/config.c
View File

@ -29,15 +29,15 @@
static struct mcf_platform_uart m528x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.mapbase = MCFUART_BASE1,
.irq = MCFINT_VECBASE + MCFINT_UART0,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.mapbase = MCFUART_BASE2,
.irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.mapbase = MCFUART_BASE3,
.irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
},
{ },
@ -51,8 +51,8 @@ static struct platform_device m528x_uart = {
static struct resource m528x_fec_resources[] = {
{
.start = MCF_MBAR + 0x1000,
.end = MCF_MBAR + 0x1000 + 0x7ff,
.start = MCFFEC_BASE,
.end = MCFFEC_BASE + MCFFEC_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
@ -227,9 +227,9 @@ static void __init m528x_uart_init_line(int line, int irq)
/* make sure PUAPAR is set for UART0 and UART1 */
if (line < 2) {
port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
port = readb(MCF5282_GPIO_PUAPAR);
port |= (0x03 << (line * 2));
writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR);
writeb(port, MCF5282_GPIO_PUAPAR);
}
}

210
arch/m68knommu/platform/528x/gpio.c
View File

@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 1,
.ngpio = 7,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *)MCFEPORT_EPDDR,
.podr = (void __iomem *)MCFEPORT_EPDR,
.ppdr = (void __iomem *)MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -49,9 +49,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 8,
.ngpio = 4,
},
.pddr = MCFGPTA_GPTDDR,
.podr = MCFGPTA_GPTPORT,
.ppdr = MCFGPTB_GPTPORT,
.pddr = (void __iomem *)MCFGPTA_GPTDDR,
.podr = (void __iomem *)MCFGPTA_GPTPORT,
.ppdr = (void __iomem *)MCFGPTB_GPTPORT,
},
{
.gpio_chip = {
@ -65,9 +65,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 4,
},
.pddr = MCFGPTB_GPTDDR,
.podr = MCFGPTB_GPTPORT,
.ppdr = MCFGPTB_GPTPORT,
.pddr = (void __iomem *)MCFGPTB_GPTDDR,
.podr = (void __iomem *)MCFGPTB_GPTPORT,
.ppdr = (void __iomem *)MCFGPTB_GPTPORT,
},
{
.gpio_chip = {
@ -81,9 +81,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 24,
.ngpio = 4,
},
.pddr = MCFQADC_DDRQA,
.podr = MCFQADC_PORTQA,
.ppdr = MCFQADC_PORTQA,
.pddr = (void __iomem *)MCFQADC_DDRQA,
.podr = (void __iomem *)MCFQADC_PORTQA,
.ppdr = (void __iomem *)MCFQADC_PORTQA,
},
{
.gpio_chip = {
@ -97,9 +97,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 4,
},
.pddr = MCFQADC_DDRQB,
.podr = MCFQADC_PORTQB,
.ppdr = MCFQADC_PORTQB,
.pddr = (void __iomem *)MCFQADC_DDRQB,
.podr = (void __iomem *)MCFQADC_PORTQB,
.ppdr = (void __iomem *)MCFQADC_PORTQB,
},
{
.gpio_chip = {
@ -113,11 +113,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRA,
.podr = MCFGPIO_PORTA,
.ppdr = MCFGPIO_PORTAP,
.setr = MCFGPIO_SETA,
.clrr = MCFGPIO_CLRA,
.pddr = (void __iomem *)MCFGPIO_DDRA,
.podr = (void __iomem *)MCFGPIO_PORTA,
.ppdr = (void __iomem *)MCFGPIO_PORTAP,
.setr = (void __iomem *)MCFGPIO_SETA,
.clrr = (void __iomem *)MCFGPIO_CLRA,
},
{
.gpio_chip = {
@ -131,11 +131,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 48,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRB,
.podr = MCFGPIO_PORTB,
.ppdr = MCFGPIO_PORTBP,
.setr = MCFGPIO_SETB,
.clrr = MCFGPIO_CLRB,
.pddr = (void __iomem *)MCFGPIO_DDRB,
.podr = (void __iomem *)MCFGPIO_PORTB,
.ppdr = (void __iomem *)MCFGPIO_PORTBP,
.setr = (void __iomem *)MCFGPIO_SETB,
.clrr = (void __iomem *)MCFGPIO_CLRB,
},
{
.gpio_chip = {
@ -149,11 +149,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 56,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRC,
.podr = MCFGPIO_PORTC,
.ppdr = MCFGPIO_PORTCP,
.setr = MCFGPIO_SETC,
.clrr = MCFGPIO_CLRC,
.pddr = (void __iomem *)MCFGPIO_DDRC,
.podr = (void __iomem *)MCFGPIO_PORTC,
.ppdr = (void __iomem *)MCFGPIO_PORTCP,
.setr = (void __iomem *)MCFGPIO_SETC,
.clrr = (void __iomem *)MCFGPIO_CLRC,
},
{
.gpio_chip = {
@ -167,11 +167,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRD,
.podr = MCFGPIO_PORTD,
.ppdr = MCFGPIO_PORTDP,
.setr = MCFGPIO_SETD,
.clrr = MCFGPIO_CLRD,
.pddr = (void __iomem *)MCFGPIO_DDRD,
.podr = (void __iomem *)MCFGPIO_PORTD,
.ppdr = (void __iomem *)MCFGPIO_PORTDP,
.setr = (void __iomem *)MCFGPIO_SETD,
.clrr = (void __iomem *)MCFGPIO_CLRD,
},
{
.gpio_chip = {
@ -185,11 +185,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRE,
.podr = MCFGPIO_PORTE,
.ppdr = MCFGPIO_PORTEP,
.setr = MCFGPIO_SETE,
.clrr = MCFGPIO_CLRE,
.pddr = (void __iomem *)MCFGPIO_DDRE,
.podr = (void __iomem *)MCFGPIO_PORTE,
.ppdr = (void __iomem *)MCFGPIO_PORTEP,
.setr = (void __iomem *)MCFGPIO_SETE,
.clrr = (void __iomem *)MCFGPIO_CLRE,
},
{
.gpio_chip = {
@ -203,11 +203,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 80,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRF,
.podr = MCFGPIO_PORTF,
.ppdr = MCFGPIO_PORTFP,
.setr = MCFGPIO_SETF,
.clrr = MCFGPIO_CLRF,
.pddr = (void __iomem *)MCFGPIO_DDRF,
.podr = (void __iomem *)MCFGPIO_PORTF,
.ppdr = (void __iomem *)MCFGPIO_PORTFP,
.setr = (void __iomem *)MCFGPIO_SETF,
.clrr = (void __iomem *)MCFGPIO_CLRF,
},
{
.gpio_chip = {
@ -221,11 +221,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 88,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRG,
.podr = MCFGPIO_PORTG,
.ppdr = MCFGPIO_PORTGP,
.setr = MCFGPIO_SETG,
.clrr = MCFGPIO_CLRG,
.pddr = (void __iomem *)MCFGPIO_DDRG,
.podr = (void __iomem *)MCFGPIO_PORTG,
.ppdr = (void __iomem *)MCFGPIO_PORTGP,
.setr = (void __iomem *)MCFGPIO_SETG,
.clrr = (void __iomem *)MCFGPIO_CLRG,
},
{
.gpio_chip = {
@ -239,11 +239,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 96,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRH,
.podr = MCFGPIO_PORTH,
.ppdr = MCFGPIO_PORTHP,
.setr = MCFGPIO_SETH,
.clrr = MCFGPIO_CLRH,
.pddr = (void __iomem *)MCFGPIO_DDRH,
.podr = (void __iomem *)MCFGPIO_PORTH,
.ppdr = (void __iomem *)MCFGPIO_PORTHP,
.setr = (void __iomem *)MCFGPIO_SETH,
.clrr = (void __iomem *)MCFGPIO_CLRH,
},
{
.gpio_chip = {
@ -257,11 +257,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 104,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRJ,
.podr = MCFGPIO_PORTJ,
.ppdr = MCFGPIO_PORTJP,
.setr = MCFGPIO_SETJ,
.clrr = MCFGPIO_CLRJ,
.pddr = (void __iomem *)MCFGPIO_DDRJ,
.podr = (void __iomem *)MCFGPIO_PORTJ,
.ppdr = (void __iomem *)MCFGPIO_PORTJP,
.setr = (void __iomem *)MCFGPIO_SETJ,
.clrr = (void __iomem *)MCFGPIO_CLRJ,
},
{
.gpio_chip = {
@ -275,11 +275,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 112,
.ngpio = 8,
},
.pddr = MCFGPIO_DDRDD,
.podr = MCFGPIO_PORTDD,
.ppdr = MCFGPIO_PORTDDP,
.setr = MCFGPIO_SETDD,
.clrr = MCFGPIO_CLRDD,
.pddr = (void __iomem *)MCFGPIO_DDRDD,
.podr = (void __iomem *)MCFGPIO_PORTDD,
.ppdr = (void __iomem *)MCFGPIO_PORTDDP,
.setr = (void __iomem *)MCFGPIO_SETDD,
.clrr = (void __iomem *)MCFGPIO_CLRDD,
},
{
.gpio_chip = {
@ -293,11 +293,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 120,
.ngpio = 8,
},
.pddr = MCFGPIO_DDREH,
.podr = MCFGPIO_PORTEH,
.ppdr = MCFGPIO_PORTEHP,
.setr = MCFGPIO_SETEH,
.clrr = MCFGPIO_CLREH,
.pddr = (void __iomem *)MCFGPIO_DDREH,
.podr = (void __iomem *)MCFGPIO_PORTEH,
.ppdr = (void __iomem *)MCFGPIO_PORTEHP,
.setr = (void __iomem *)MCFGPIO_SETEH,
.clrr = (void __iomem *)MCFGPIO_CLREH,
},
{
.gpio_chip = {
@ -311,11 +311,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 128,
.ngpio = 8,
},
.pddr = MCFGPIO_DDREL,
.podr = MCFGPIO_PORTEL,
.ppdr = MCFGPIO_PORTELP,
.setr = MCFGPIO_SETEL,
.clrr = MCFGPIO_CLREL,
.pddr = (void __iomem *)MCFGPIO_DDREL,
.podr = (void __iomem *)MCFGPIO_PORTEL,
.ppdr = (void __iomem *)MCFGPIO_PORTELP,
.setr = (void __iomem *)MCFGPIO_SETEL,
.clrr = (void __iomem *)MCFGPIO_CLREL,
},
{
.gpio_chip = {
@ -329,11 +329,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 136,
.ngpio = 6,
},
.pddr = MCFGPIO_DDRAS,
.podr = MCFGPIO_PORTAS,
.ppdr = MCFGPIO_PORTASP,
.setr = MCFGPIO_SETAS,
.clrr = MCFGPIO_CLRAS,
.pddr = (void __iomem *)MCFGPIO_DDRAS,
.podr = (void __iomem *)MCFGPIO_PORTAS,
.ppdr = (void __iomem *)MCFGPIO_PORTASP,
.setr = (void __iomem *)MCFGPIO_SETAS,
.clrr = (void __iomem *)MCFGPIO_CLRAS,
},
{
.gpio_chip = {
@ -347,11 +347,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 144,
.ngpio = 7,
},
.pddr = MCFGPIO_DDRQS,
.podr = MCFGPIO_PORTQS,
.ppdr = MCFGPIO_PORTQSP,
.setr = MCFGPIO_SETQS,
.clrr = MCFGPIO_CLRQS,
.pddr = (void __iomem *)MCFGPIO_DDRQS,
.podr = (void __iomem *)MCFGPIO_PORTQS,
.ppdr = (void __iomem *)MCFGPIO_PORTQSP,
.setr = (void __iomem *)MCFGPIO_SETQS,
.clrr = (void __iomem *)MCFGPIO_CLRQS,
},
{
.gpio_chip = {
@ -365,11 +365,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 152,
.ngpio = 6,
},
.pddr = MCFGPIO_DDRSD,
.podr = MCFGPIO_PORTSD,
.ppdr = MCFGPIO_PORTSDP,
.setr = MCFGPIO_SETSD,
.clrr = MCFGPIO_CLRSD,
.pddr = (void __iomem *)MCFGPIO_DDRSD,
.podr = (void __iomem *)MCFGPIO_PORTSD,
.ppdr = (void __iomem *)MCFGPIO_PORTSDP,
.setr = (void __iomem *)MCFGPIO_SETSD,
.clrr = (void __iomem *)MCFGPIO_CLRSD,
},
{
.gpio_chip = {
@ -383,11 +383,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 160,
.ngpio = 4,
},
.pddr = MCFGPIO_DDRTC,
.podr = MCFGPIO_PORTTC,
.ppdr = MCFGPIO_PORTTCP,
.setr = MCFGPIO_SETTC,
.clrr = MCFGPIO_CLRTC,
.pddr = (void __iomem *)MCFGPIO_DDRTC,
.podr = (void __iomem *)MCFGPIO_PORTTC,
.ppdr = (void __iomem *)MCFGPIO_PORTTCP,
.setr = (void __iomem *)MCFGPIO_SETTC,
.clrr = (void __iomem *)MCFGPIO_CLRTC,
},
{
.gpio_chip = {
@ -401,11 +401,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 168,
.ngpio = 4,
},
.pddr = MCFGPIO_DDRTD,
.podr = MCFGPIO_PORTTD,
.ppdr = MCFGPIO_PORTTDP,
.setr = MCFGPIO_SETTD,
.clrr = MCFGPIO_CLRTD,
.pddr = (void __iomem *)MCFGPIO_DDRTD,
.podr = (void __iomem *)MCFGPIO_PORTTD,
.ppdr = (void __iomem *)MCFGPIO_PORTTDP,
.setr = (void __iomem *)MCFGPIO_SETTD,
.clrr = (void __iomem *)MCFGPIO_CLRTD,
},
{
.gpio_chip = {
@ -419,11 +419,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 176,
.ngpio = 4,
},
.pddr = MCFGPIO_DDRUA,
.podr = MCFGPIO_PORTUA,
.ppdr = MCFGPIO_PORTUAP,
.setr = MCFGPIO_SETUA,
.clrr = MCFGPIO_CLRUA,
.pddr = (void __iomem *)MCFGPIO_DDRUA,
.podr = (void __iomem *)MCFGPIO_PORTUA,
.ppdr = (void __iomem *)MCFGPIO_PORTUAP,
.setr = (void __iomem *)MCFGPIO_SETUA,
.clrr = (void __iomem *)MCFGPIO_CLRUA,
},
};

6
arch/m68knommu/platform/5307/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 16,
},
.pddr = MCFSIM_PADDR,
.podr = MCFSIM_PADAT,
.ppdr = MCFSIM_PADAT,
.pddr = (void __iomem *) MCFSIM_PADDR,
.podr = (void __iomem *) MCFSIM_PADAT,
.ppdr = (void __iomem *) MCFSIM_PADAT,
},
};

166
arch/m68knommu/platform/532x/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 8,
},
.pddr = MCFEPORT_EPDDR,
.podr = MCFEPORT_EPDR,
.ppdr = MCFEPORT_EPPDR,
.pddr = (void __iomem *) MCFEPORT_EPDDR,
.podr = (void __iomem *) MCFEPORT_EPDR,
.ppdr = (void __iomem *) MCFEPORT_EPPDR,
},
{
.gpio_chip = {
@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 8,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FECH,
.podr = MCFGPIO_PODR_FECH,
.ppdr = MCFGPIO_PPDSDR_FECH,
.setr = MCFGPIO_PPDSDR_FECH,
.clrr = MCFGPIO_PCLRR_FECH,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECH,
.podr = (void __iomem *) MCFGPIO_PODR_FECH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECH,
},
{
.gpio_chip = {
@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 16,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_FECL,
.podr = MCFGPIO_PODR_FECL,
.ppdr = MCFGPIO_PPDSDR_FECL,
.setr = MCFGPIO_PPDSDR_FECL,
.clrr = MCFGPIO_PCLRR_FECL,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECL,
.podr = (void __iomem *) MCFGPIO_PODR_FECL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECL,
},
{
.gpio_chip = {
@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 24,
.ngpio = 5,
},
.pddr = MCFGPIO_PDDR_SSI,
.podr = MCFGPIO_PODR_SSI,
.ppdr = MCFGPIO_PPDSDR_SSI,
.setr = MCFGPIO_PPDSDR_SSI,
.clrr = MCFGPIO_PCLRR_SSI,
.pddr = (void __iomem *) MCFGPIO_PDDR_SSI,
.podr = (void __iomem *) MCFGPIO_PODR_SSI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_SSI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_SSI,
},
{
.gpio_chip = {
@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 32,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BUSCTL,
.podr = MCFGPIO_PODR_BUSCTL,
.ppdr = MCFGPIO_PPDSDR_BUSCTL,
.setr = MCFGPIO_PPDSDR_BUSCTL,
.clrr = MCFGPIO_PCLRR_BUSCTL,
.pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
.podr = (void __iomem *) MCFGPIO_PODR_BUSCTL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
},
{
.gpio_chip = {
@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 40,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_BE,
.podr = MCFGPIO_PODR_BE,
.ppdr = MCFGPIO_PPDSDR_BE,
.setr = MCFGPIO_PPDSDR_BE,
.clrr = MCFGPIO_PCLRR_BE,
.pddr = (void __iomem *) MCFGPIO_PDDR_BE,
.podr = (void __iomem *) MCFGPIO_PODR_BE,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE,
.setr = (void __iomem *) MCFGPIO_PPDSDR_BE,
.clrr = (void __iomem *) MCFGPIO_PCLRR_BE,
},
{
.gpio_chip = {
@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 49,
.ngpio = 5,
},
.pddr = MCFGPIO_PDDR_CS,
.podr = MCFGPIO_PODR_CS,
.ppdr = MCFGPIO_PPDSDR_CS,
.setr = MCFGPIO_PPDSDR_CS,
.clrr = MCFGPIO_PCLRR_CS,
.pddr = (void __iomem *) MCFGPIO_PDDR_CS,
.podr = (void __iomem *) MCFGPIO_PODR_CS,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.setr = (void __iomem *) MCFGPIO_PPDSDR_CS,
.clrr = (void __iomem *) MCFGPIO_PCLRR_CS,
},
{
.gpio_chip = {
@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 58,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_PWM,
.podr = MCFGPIO_PODR_PWM,
.ppdr = MCFGPIO_PPDSDR_PWM,
.setr = MCFGPIO_PPDSDR_PWM,
.clrr = MCFGPIO_PCLRR_PWM,
.pddr = (void __iomem *) MCFGPIO_PDDR_PWM,
.podr = (void __iomem *) MCFGPIO_PODR_PWM,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
.setr = (void __iomem *) MCFGPIO_PPDSDR_PWM,
.clrr = (void __iomem *) MCFGPIO_PCLRR_PWM,
},
{
.gpio_chip = {
@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 64,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_FECI2C,
.podr = MCFGPIO_PODR_FECI2C,
.ppdr = MCFGPIO_PPDSDR_FECI2C,
.setr = MCFGPIO_PPDSDR_FECI2C,
.clrr = MCFGPIO_PCLRR_FECI2C,
.pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C,
.podr = (void __iomem *) MCFGPIO_PODR_FECI2C,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.setr = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
.clrr = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
},
{
.gpio_chip = {
@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 72,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_UART,
.podr = MCFGPIO_PODR_UART,
.ppdr = MCFGPIO_PPDSDR_UART,
.setr = MCFGPIO_PPDSDR_UART,
.clrr = MCFGPIO_PCLRR_UART,
.pddr = (void __iomem *) MCFGPIO_PDDR_UART,
.podr = (void __iomem *) MCFGPIO_PODR_UART,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_UART,
.setr = (void __iomem *) MCFGPIO_PPDSDR_UART,
.clrr = (void __iomem *) MCFGPIO_PCLRR_UART,
},
{
.gpio_chip = {
@ -210,11 +210,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 80,
.ngpio = 6,
},
.pddr = MCFGPIO_PDDR_QSPI,
.podr = MCFGPIO_PODR_QSPI,
.ppdr = MCFGPIO_PPDSDR_QSPI,
.setr = MCFGPIO_PPDSDR_QSPI,
.clrr = MCFGPIO_PCLRR_QSPI,
.pddr = (void __iomem *) MCFGPIO_PDDR_QSPI,
.podr = (void __iomem *) MCFGPIO_PODR_QSPI,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.setr = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
.clrr = (void __iomem *) MCFGPIO_PCLRR_QSPI,
},
{
.gpio_chip = {
@ -228,11 +228,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 88,
.ngpio = 4,
},
.pddr = MCFGPIO_PDDR_TIMER,
.podr = MCFGPIO_PODR_TIMER,
.ppdr = MCFGPIO_PPDSDR_TIMER,
.setr = MCFGPIO_PPDSDR_TIMER,
.clrr = MCFGPIO_PCLRR_TIMER,
.pddr = (void __iomem *) MCFGPIO_PDDR_TIMER,
.podr = (void __iomem *) MCFGPIO_PODR_TIMER,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.setr = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
.clrr = (void __iomem *) MCFGPIO_PCLRR_TIMER,
},
{
.gpio_chip = {
@ -246,11 +246,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 96,
.ngpio = 2,
},
.pddr = MCFGPIO_PDDR_LCDDATAH,
.podr = MCFGPIO_PODR_LCDDATAH,
.ppdr = MCFGPIO_PPDSDR_LCDDATAH,
.setr = MCFGPIO_PPDSDR_LCDDATAH,
.clrr = MCFGPIO_PCLRR_LCDDATAH,
.pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
.podr = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
},
{
.gpio_chip = {
@ -264,11 +264,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 104,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_LCDDATAM,
.podr = MCFGPIO_PODR_LCDDATAM,
.ppdr = MCFGPIO_PPDSDR_LCDDATAM,
.setr = MCFGPIO_PPDSDR_LCDDATAM,
.clrr = MCFGPIO_PCLRR_LCDDATAM,
.pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
.podr = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
.setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
.clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
},
{
.gpio_chip = {
@ -282,11 +282,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 112,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_LCDDATAL,
.podr = MCFGPIO_PODR_LCDDATAL,
.ppdr = MCFGPIO_PPDSDR_LCDDATAL,
.setr = MCFGPIO_PPDSDR_LCDDATAL,
.clrr = MCFGPIO_PCLRR_LCDDATAL,
.pddr = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
.podr = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
},
{
.gpio_chip = {
@ -300,11 +300,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 120,
.ngpio = 1,
},
.pddr = MCFGPIO_PDDR_LCDCTLH,
.podr = MCFGPIO_PODR_LCDCTLH,
.ppdr = MCFGPIO_PPDSDR_LCDCTLH,
.setr = MCFGPIO_PPDSDR_LCDCTLH,
.clrr = MCFGPIO_PCLRR_LCDCTLH,
.pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
.podr = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
.setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
.clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
},
{
.gpio_chip = {
@ -318,11 +318,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.base = 128,
.ngpio = 8,
},
.pddr = MCFGPIO_PDDR_LCDCTLL,
.podr = MCFGPIO_PODR_LCDCTLL,
.ppdr = MCFGPIO_PPDSDR_LCDCTLL,
.setr = MCFGPIO_PPDSDR_LCDCTLL,
.clrr = MCFGPIO_PCLRR_LCDCTLL,
.pddr = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
.podr = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
.ppdr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
.setr = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
.clrr = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
},
};

6
arch/m68knommu/platform/5407/gpio.c
View File

@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
.set = mcf_gpio_set_value,
.ngpio = 16,
},
.pddr = MCFSIM_PADDR,
.podr = MCFSIM_PADAT,
.ppdr = MCFSIM_PADAT,
.pddr = (void __iomem *) MCFSIM_PADDR,
.podr = (void __iomem *) MCFSIM_PADAT,
.ppdr = (void __iomem *) MCFSIM_PADAT,
},
};

1
arch/m68knommu/platform/54xx/Makefile
View File

@ -15,4 +15,5 @@
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
obj-$(CONFIG_FIREBEE) += firebee.o

86
arch/m68knommu/platform/54xx/firebee.c Normal file
View File

@ -0,0 +1,86 @@
/***************************************************************************/
/*
* firebee.c -- extra startup code support for the FireBee boards
*
* Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* 8MB of NOR flash fitted to the FireBee board.
*/
#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */
#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */
#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
#define PART_BOOT_SIZE 0x00040000 /* 256k in size */
#define PART_IMAGE_START 0x00040000 /* Start after boot loader */
#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */
#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */
static struct mtd_partition firebee_flash_parts[] = {
{
.name = "dBUG",
.offset = PART_BOOT_START,
.size = PART_BOOT_SIZE,
},
{
.name = "FPGA",
.offset = PART_FPGA_START,
.size = PART_FPGA_SIZE,
},
{
.name = "image",
.offset = PART_IMAGE_START,
.size = PART_IMAGE_SIZE,
},
};
static struct physmap_flash_data firebee_flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(firebee_flash_parts),
.parts = firebee_flash_parts,
};
static struct resource firebee_flash_resource = {
.start = FLASH_PHYS_ADDR,
.end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device firebee_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &firebee_flash_data,
},
.num_resources = 1,
.resource = &firebee_flash_resource,
};
/***************************************************************************/
static int __init init_firebee(void)
{
platform_device_register(&firebee_flash);
return 0;
}
arch_initcall(init_firebee);
/***************************************************************************/

12
arch/m68knommu/platform/68328/ints.c
View File

@ -135,20 +135,20 @@ void process_int(int vec, struct pt_regs *fp)
}
}
static void intc_irq_unmask(unsigned int irq)
static void intc_irq_unmask(struct irq_data *d)
{
IMR &= ~(1<<irq);
IMR &= ~(1 << d->irq);
}
static void intc_irq_mask(unsigned int irq)
static void intc_irq_mask(struct irq_data *d)
{
IMR |= (1<<irq);
IMR |= (1 << d->irq);
}
static struct irq_chip intc_irq_chip = {
.name = "M68K-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
/*

18
arch/m68knommu/platform/68360/ints.c
View File

@ -37,26 +37,26 @@ extern void *_ramvec[];
/* The number of spurious interrupts */
volatile unsigned int num_spurious;
static void intc_irq_unmask(unsigned int irq)
static void intc_irq_unmask(struct irq_data *d)
{
pquicc->intr_cimr |= (1 << irq);
pquicc->intr_cimr |= (1 << d->irq);
}
static void intc_irq_mask(unsigned int irq)
static void intc_irq_mask(struct irq_data *d)
{
pquicc->intr_cimr &= ~(1 << irq);
pquicc->intr_cimr &= ~(1 << d->irq);
}
static void intc_irq_ack(unsigned int irq)
static void intc_irq_ack(struct irq_data *d)
{
pquicc->intr_cisr = (1 << irq);
pquicc->intr_cisr = (1 << d->irq);
}
static struct irq_chip intc_irq_chip = {
.name = "M68K-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.ack = intc_irq_ack,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_ack = intc_irq_ack,
};
/*

8
arch/m68knommu/platform/coldfire/dma.c
View File

@ -21,16 +21,16 @@
*/
unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
#ifdef MCFDMA_BASE0
MCF_MBAR + MCFDMA_BASE0,
MCFDMA_BASE0,
#endif
#ifdef MCFDMA_BASE1
MCF_MBAR + MCFDMA_BASE1,
MCFDMA_BASE1,
#endif
#ifdef MCFDMA_BASE2
MCF_MBAR + MCFDMA_BASE2,
MCFDMA_BASE2,
#endif
#ifdef MCFDMA_BASE3
MCF_MBAR + MCFDMA_BASE3,
MCFDMA_BASE3,
#endif
};

10
arch/m68knommu/platform/coldfire/head.S
View File

@ -41,17 +41,17 @@
* DRAM controller is quite different.
*/
.macro GET_MEM_SIZE
movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
btst #0,%d0 /* check if region enabled */
beq 1f
andl #0xfffc0000,%d0
beq 1f
addl #0x00040000,%d0 /* convert mask to size */
1:
movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
btst #0,%d1 /* check if region enabled */
beq 2f
andl #0xfffc0000, %d1
andl #0xfffc0000,%d1
beq 2f
addl #0x00040000,%d1
addl %d1,%d0 /* total mem size in d0 */
@ -68,14 +68,14 @@
#elif defined(CONFIG_M520x)
.macro GET_MEM_SIZE
clrl %d0
movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
andl #0x1f, %d2 /* Get only the chip select size */
beq 3f /* Check if it is enabled */
addql #1, %d2 /* Form exponent */
moveql #1, %d0
lsll %d2, %d0 /* 2 ^ exponent */
3:
movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
andl #0x1f, %d2 /* Get only the chip select size */
beq 4f /* Check if it is enabled */
addql #1, %d2 /* Form exponent */

180
arch/m68knommu/platform/coldfire/intc-2.c
View File

@ -7,7 +7,10 @@
* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
* controllers, and the 547x and 548x families which have only one of them.
*
* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
* The external 7 fixed interrupts are part the the Edge Port unit of these
* ColdFire parts. They can be configured as level or edge triggered.
*
* (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
@ -31,11 +34,12 @@
#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
/*
* Each vector needs a unique priority and level associated with it.
* We don't really care so much what they are, we don't rely on the
* traditional priority interrupt scheme of the m68k/ColdFire.
* The EDGE Port interrupts are the fixed 7 external interrupts.
* They need some special treatment, for example they need to be acked.
*/
static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT7 71 /* EDGE Port interrupt 7 */
#ifdef MCFICM_INTC1
#define NR_VECS 128
@ -43,66 +47,147 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
#define NR_VECS 64
#endif
static void intc_irq_mask(unsigned int irq)
static void intc_irq_mask(struct irq_data *d)
{
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
unsigned long imraddr;
u32 val, imrbit;
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long imraddr;
u32 val, imrbit;
irq -= MCFINT_VECBASE;
imraddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
imraddr += MCFICM_INTC0;
imraddr = MCFICM_INTC0;
#endif
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
val = __raw_readl(imraddr);
__raw_writel(val | imrbit, imraddr);
}
val = __raw_readl(imraddr);
__raw_writel(val | imrbit, imraddr);
}
static void intc_irq_unmask(unsigned int irq)
static void intc_irq_unmask(struct irq_data *d)
{
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
unsigned long intaddr, imraddr, icraddr;
u32 val, imrbit;
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long imraddr;
u32 val, imrbit;
irq -= MCFINT_VECBASE;
intaddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
intaddr += MCFICM_INTC0;
imraddr = MCFICM_INTC0;
#endif
imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
imrbit = 0x1 << (irq & 0x1f);
imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
imrbit = 0x1 << (irq & 0x1f);
/* Don't set the "maskall" bit! */
if ((irq & 0x20) == 0)
imrbit |= 0x1;
/* Don't set the "maskall" bit! */
if ((irq & 0x20) == 0)
imrbit |= 0x1;
if (__raw_readb(icraddr) == 0)
__raw_writeb(intc_intpri--, icraddr);
val = __raw_readl(imraddr);
__raw_writel(val & ~imrbit, imraddr);
}
val = __raw_readl(imraddr);
__raw_writel(val & ~imrbit, imraddr);
}
static int intc_irq_set_type(unsigned int irq, unsigned int type)
/*
* Only the external (or EDGE Port) interrupts need to be acknowledged
* here, as part of the IRQ handler. They only really need to be ack'ed
* if they are in edge triggered mode, but there is no harm in doing it
* for all types.
*/
static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
__raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
}
/*
* Each vector needs a unique priority and level associated with it.
* We don't really care so much what they are, we don't rely on the
* traditional priority interrupt scheme of the m68k/ColdFire. This
* only needs to be set once for an interrupt, and we will never change
* these values once we have set them.
*/
static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
static unsigned int intc_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long icraddr;
#ifdef MCFICM_INTC1
icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
icraddr = MCFICM_INTC0;
#endif
icraddr += MCFINTC_ICR0 + (irq & 0x3f);
if (__raw_readb(icraddr) == 0)
__raw_writeb(intc_intpri--, icraddr);
irq = d->irq;
if ((irq >= EINT1) && (irq <= EINT7)) {
u8 v;
irq -= EINT0;
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
}
intc_irq_unmask(d);
return 0;
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
/* Level triggered */
tb = 0;
break;
}
if (tb)
set_irq_handler(irq, handle_edge_irq);
irq -= EINT0;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.set_type = intc_irq_set_type,
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
static struct irq_chip intc_irq_chip_edge_port = {
.name = "CF-INTC-EP",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
@ -112,13 +197,16 @@ void __init init_IRQ(void)
init_vectors();
/* Mask all interrupt sources */
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
#endif
for (irq = 0; (irq < NR_IRQS); irq++) {
set_irq_chip(irq, &intc_irq_chip);
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
if ((irq >= EINT1) && (irq <=EINT7))
set_irq_chip(irq, &intc_irq_chip_edge_port);
else
set_irq_chip(irq, &intc_irq_chip);
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}

167
arch/m68knommu/platform/coldfire/intc-simr.c
View File

@ -3,7 +3,7 @@
*
* Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
*
* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
* (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
@ -20,47 +20,156 @@
#include <asm/mcfsim.h>
#include <asm/traps.h>
static void intc_irq_mask(unsigned int irq)
/*
* The EDGE Port interrupts are the fixed 7 external interrupts.
* They need some special treatment, for example they need to be acked.
*/
#ifdef CONFIG_M520x
/*
* The 520x parts only support a limited range of these external
* interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
*/
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT4 66 /* EDGE Port interrupt 4 */
#define EINT7 67 /* EDGE Port interrupt 7 */
static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
static unsigned int inline irq2ebit(unsigned int irq)
{
if (irq >= MCFINT_VECBASE) {
if (irq < MCFINT_VECBASE + 64)
__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
}
return irqebitmap[irq - EINT0];
}
static void intc_irq_unmask(unsigned int irq)
#else
/*
* Most of the ColdFire parts with the EDGE Port module just have
* a strait direct mapping of the 7 external interrupts. Although
* there is a bit reserved for 0, it is not used.
*/
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT7 71 /* EDGE Port interrupt 7 */
static unsigned int inline irq2ebit(unsigned int irq)
{
if (irq >= MCFINT_VECBASE) {
if (irq < MCFINT_VECBASE + 64)
__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
}
return irq - EINT0;
}
static int intc_irq_set_type(unsigned int irq, unsigned int type)
#endif
/*
* There maybe one or two interrupt control units, each has 64
* interrupts. If there is no second unit then MCFINTC1_* defines
* will be 0 (and code for them optimized away).
*/
static void intc_irq_mask(struct irq_data *d)
{
if (irq >= MCFINT_VECBASE) {
if (irq < MCFINT_VECBASE + 64)
__raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
__raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC1_SIMR && (irq > 64))
__raw_writeb(irq - 64, MCFINTC1_SIMR);
else
__raw_writeb(irq, MCFINTC0_SIMR);
}
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC1_CIMR && (irq > 64))
__raw_writeb(irq - 64, MCFINTC1_CIMR);
else
__raw_writeb(irq, MCFINTC0_CIMR);
}
static void intc_irq_ack(struct irq_data *d)
{
unsigned int ebit = irq2ebit(d->irq);
__raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
}
static unsigned int intc_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= EINT1) && (irq <= EINT7)) {
unsigned int ebit = irq2ebit(irq);
u8 v;
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
}
irq -= MCFINT_VECBASE;
if (MCFINTC1_ICR0 && (irq > 64))
__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
else
__raw_writeb(5, MCFINTC0_ICR0 + irq);
intc_irq_unmask(d);
return 0;
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int ebit, irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
/* Level triggered */
tb = 0;
break;
}
if (tb)
set_irq_handler(irq, handle_edge_irq);
ebit = irq2ebit(irq) * 2;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.set_type = intc_irq_set_type,
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
static struct irq_chip intc_irq_chip_edge_port = {
.name = "CF-INTC-EP",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq;
int irq, eirq;
init_vectors();
@ -69,8 +178,12 @@ void __init init_IRQ(void)
if (MCFINTC1_SIMR)
__raw_writeb(0xff, MCFINTC1_SIMR);
for (irq = 0; (irq < NR_IRQS); irq++) {
set_irq_chip(irq, &intc_irq_chip);
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
if ((irq >= EINT1) && (irq <= EINT7))
set_irq_chip(irq, &intc_irq_chip_edge_port);
else
set_irq_chip(irq, &intc_irq_chip);
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}

20
arch/m68knommu/platform/coldfire/intc.c
View File

@ -111,28 +111,28 @@ void mcf_autovector(int irq)
#endif
}
static void intc_irq_mask(unsigned int irq)
static void intc_irq_mask(struct irq_data *d)
{
if (mcf_irq2imr[irq])
mcf_setimr(mcf_irq2imr[irq]);
if (mcf_irq2imr[d->irq])
mcf_setimr(mcf_irq2imr[d->irq]);
}
static void intc_irq_unmask(unsigned int irq)
static void intc_irq_unmask(struct irq_data *d)
{
if (mcf_irq2imr[irq])
mcf_clrimr(mcf_irq2imr[irq]);
if (mcf_irq2imr[d->irq])
mcf_clrimr(mcf_irq2imr[d->irq]);
}
static int intc_irq_set_type(unsigned int irq, unsigned int type)
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.set_type = intc_irq_set_type,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)

2
arch/m68knommu/platform/coldfire/pit.c
View File

@ -31,7 +31,7 @@
* By default use timer1 as the system clock timer.
*/
#define FREQ ((MCF_CLK / 2) / 64)
#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
#define TA(a) (MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt;

4
arch/m68knommu/platform/coldfire/timers.c
View File

@ -28,7 +28,7 @@
* By default use timer1 as the system clock timer.
*/
#define FREQ (MCF_BUSCLK / 16)
#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
#define TA(a) (MCFTIMER_BASE1 + (a))
/*
* These provide the underlying interrupt vector support.
@ -126,7 +126,7 @@ void hw_timer_init(void)
/*
* By default use timer2 as the profiler clock timer.
*/
#define PA(a) (MCF_MBAR + MCFTIMER_BASE2 + (a))
#define PA(a) (MCFTIMER_BASE2 + (a))
/*
* Choose a reasonably fast profile timer. Make it an odd value to