CRIS: Drop code related to obsolete or unused kconfigs
Drop all code related to Kconfigs that don't exist. Fix one Kconfig where it was actually typo:ed (ETRAX_KGB_PORT2) Drop content related to CRIS v32 SoCs from etraxgpio.h headerfile, all use of GPIO for both ETRAX FS and ARTPEC-3 should now be through standard gpiolib instead. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
This commit is contained in:
Jesper Nilsson
parent
9f4137fa2c
commit
e301a08be4
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@ -354,63 +354,6 @@ no_command_line:
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blo 1b
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nop
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#ifdef CONFIG_BLK_DEV_ETRAXIDE
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;; disable ATA before enabling it in genconfig below
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moveq 0,$r0
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move.d $r0,[R_ATA_CTRL_DATA]
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move.d $r0,[R_ATA_TRANSFER_CNT]
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move.d $r0,[R_ATA_CONFIG]
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#if 0
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move.d R_PORT_G_DATA, $r1
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move.d $r0, [$r1]; assert ATA bus-reset
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nop
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nop
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nop
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nop
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nop
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nop
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move.d 0x08000000,$r0
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move.d $r0,[$r1]
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#endif
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#endif
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#ifdef CONFIG_JULIETTE
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;; configure external DMA channel 0 before enabling it in genconfig
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moveq 0,$r0
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move.d $r0,[R_EXT_DMA_0_ADDR]
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; cnt enable, word size, output, stop, size 0
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move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \
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| IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \
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| IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \
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| IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \
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| IO_STATE (R_EXT_DMA_0_CMD, wid, word) \
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| IO_STATE (R_EXT_DMA_0_CMD, dir, output) \
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| IO_STATE (R_EXT_DMA_0_CMD, run, stop) \
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| IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0
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move.d $r0,[R_EXT_DMA_0_CMD]
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;; reset dma4 and wait for completion
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moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
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move.b $r0,[R_DMA_CH4_CMD]
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1: move.b [R_DMA_CH4_CMD],$r0
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and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0
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cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
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beq 1b
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nop
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;; reset dma5 and wait for completion
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moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
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move.b $r0,[R_DMA_CH5_CMD]
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1: move.b [R_DMA_CH5_CMD],$r0
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and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0
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cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
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beq 1b
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nop
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#endif
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;; Etrax product HW genconfig setup
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moveq 0,$r0
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@ -447,21 +390,6 @@ no_command_line:
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| IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0
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#endif
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#if defined(CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT)
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or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0
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#endif
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move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
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move.d $r0,[R_GEN_CONFIG]
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@ -500,19 +428,9 @@ no_command_line:
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;; including their shadow registers
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move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
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or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
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#endif
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move.b $r0,[port_pa_dir_shadow]
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move.b $r0,[R_PORT_PA_DIR]
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move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.b ~(1 << 7),$r0
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#else
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or.b (1 << 7),$r0
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#endif
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#endif
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move.b $r0,[port_pa_data_shadow]
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move.b $r0,[R_PORT_PA_DATA]
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@ -520,19 +438,9 @@ no_command_line:
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move.b $r0,[port_pb_config_shadow]
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move.b $r0,[R_PORT_PB_CONFIG]
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move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
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or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0
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#endif
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move.b $r0,[port_pb_dir_shadow]
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move.b $r0,[R_PORT_PB_DIR]
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move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.b ~(1 << 5),$r0
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#else
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or.b (1 << 5),$r0
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#endif
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#endif
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move.b $r0,[port_pb_data_shadow]
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move.b $r0,[R_PORT_PB_DATA]
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@ -541,20 +449,6 @@ no_command_line:
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move.d $r0, [R_PORT_PB_I2C]
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moveq 0,$r0
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G10)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.d ~(1 << 10),$r0
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#else
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or.d (1 << 10),$r0
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#endif
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#endif
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#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G11)
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#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
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and.d ~(1 << 11),$r0
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#else
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or.d (1 << 11),$r0
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#endif
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#endif
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move.d $r0,[port_g_data_shadow]
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move.d $r0,[R_PORT_G_DATA]
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@ -71,11 +71,7 @@ paging_init(void)
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IO_STATE(R_MMU_KSEG, seg_d, page ) |
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IO_STATE(R_MMU_KSEG, seg_c, page ) |
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IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
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#ifdef CONFIG_JULIETTE
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IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
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#else
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IO_STATE(R_MMU_KSEG, seg_a, page ) |
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#endif
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IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
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IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
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IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
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@ -92,11 +88,7 @@ paging_init(void)
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IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
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#ifdef CONFIG_JULIETTE
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
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#else
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
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#endif
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IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
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@ -77,8 +77,6 @@ static struct dbg_port *port =
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&ports[2];
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#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
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&ports[3];
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#elif defined(CONFIG_ETRAX_DEBUG_PORT4)
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&ports[4];
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#else
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NULL;
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#endif
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@ -292,11 +292,7 @@ _no_romfs_in_flash:
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;; For cramfs, partition starts with magic and length.
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;; For jffs2, a jhead is prepended which contains with magic and length.
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;; The jhead is not part of the jffs2 partition however.
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#ifndef CONFIG_ETRAXFS_SIM
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move.d __bss_start, $r0
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#else
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move.d __end, $r0
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#endif
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move.d [$r0], $r1
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cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
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beq 2f ; yes, jump
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@ -37,7 +37,7 @@
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#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT1)
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#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGB_PORT2)
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#elif defined(CONFIG_ETRAX_KGDB_PORT2)
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#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT3)
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#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
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@ -128,10 +128,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
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{I2C_BOARD_INFO("tmp100", 0x4E)},
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#ifdef CONFIG_RTC_DRV_PCF8563
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{I2C_BOARD_INFO("pcf8563", 0x51)},
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#endif
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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{I2C_BOARD_INFO("vgpio", 0x20)},
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{I2C_BOARD_INFO("vgpio", 0x21)},
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#endif
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{I2C_BOARD_INFO("pca9536", 0x41)},
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{I2C_BOARD_INFO("fnp300", 0x40)},
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@ -146,10 +142,6 @@ static struct i2c_board_info __initdata i2c_info2[] = {
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{I2C_BOARD_INFO("tmp100", 0x4C)},
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{I2C_BOARD_INFO("tmp100", 0x4D)},
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{I2C_BOARD_INFO("tmp100", 0x4E)},
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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{I2C_BOARD_INFO("vgpio", 0x20)},
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{I2C_BOARD_INFO("vgpio", 0x21)},
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#endif
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{I2C_BOARD_INFO("pca9536", 0x41)},
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{I2C_BOARD_INFO("fnp300", 0x40)},
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{I2C_BOARD_INFO("fnp300", 0x42)},
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@ -192,25 +192,6 @@ config ETRAX_DEF_GIO_PE_OUT
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Configures the initial data for the general port E bits. Most
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products should use 00000 here.
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config ETRAX_DEF_GIO_PV_OE
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hex "GIO_PV_OE"
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depends on ETRAX_VIRTUAL_GPIO
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default "0000"
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help
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Configures the direction of virtual general port V bits. 1 is out,
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0 is in. This is often totally different depending on the product
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used. These bits are used for all kinds of stuff. If you don't know
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what to use, it is always safe to put all as inputs, although
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floating inputs isn't good.
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config ETRAX_DEF_GIO_PV_OUT
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hex "GIO_PV_OUT"
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depends on ETRAX_VIRTUAL_GPIO
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default "0000"
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help
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Configures the initial data for the virtual general port V bits.
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Most products should use 0000 here.
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endmenu
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endif
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@ -281,9 +281,6 @@ wait_ser:
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#ifdef CONFIG_ETRAX_PB_LEDS
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move.b $r2, [R_PORT_PB_DATA]
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#endif
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#ifdef CONFIG_ETRAX_90000000_LEDS
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move.b $r2, [0x90000000]
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#endif
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#endif
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;; check if we got something on the serial port
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@ -45,8 +45,7 @@
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assumed that we want to share code when debugging (exposes more
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trouble). */
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#ifndef SHARE_LIB_CORE
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# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \
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&& !defined(CONFIG_SHARE_SHLIB_CORE)
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# if (defined(__KERNEL__) || !defined(RELOC_DEBUG))
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# define SHARE_LIB_CORE 0
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# else
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# define SHARE_LIB_CORE 1
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@ -11,26 +11,6 @@
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* g1-g7 and g25-g31 is both input and outputs but on different pins
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* Also note that some bits change pins depending on what interfaces
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* are enabled.
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*
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* For ETRAX FS (CONFIG_ETRAXFS):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
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* /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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*
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* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
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* /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 32 bit GPIO, input only
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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* /dev/pwm0 minor 16, PWM channel 0 on PA30
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* /dev/pwm1 minor 17, PWM channel 1 on PA31
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* /dev/pwm2 minor 18, PWM channel 2 on PB26
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* /dev/ppwm minor 19, PPWM channel
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*
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*/
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#ifndef _ASM_ETRAXGPIO_H
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#define _ASM_ETRAXGPIO_H
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@ -40,52 +20,12 @@
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#define ETRAXGPIO_IOCTYPE 43
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/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
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#ifdef CONFIG_ETRAX_ARCH_V10
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_G 3
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#define GPIO_MINOR_LAST 3
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
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#endif
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#ifdef CONFIG_ETRAXFS
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_C 3
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#define GPIO_MINOR_D 4
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#define GPIO_MINOR_E 5
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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#define GPIO_MINOR_V 6
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#define GPIO_MINOR_LAST 6
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#else
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#define GPIO_MINOR_LAST 5
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#endif
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
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#endif
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_C 3
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#define GPIO_MINOR_D 4
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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#define GPIO_MINOR_V 6
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#define GPIO_MINOR_LAST 6
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#else
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#define GPIO_MINOR_LAST 4
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#endif
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#define GPIO_MINOR_FIRST_PWM 16
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#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
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#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
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#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
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#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
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#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
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#endif
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/* supported ioctl _IOC_NR's */
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@ -139,101 +79,4 @@
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#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
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/* *arg updated with current output pins. */
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/* The following ioctl's are applicable to the PWM channels only */
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#define IO_PWM_SET_MODE 0x20
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enum io_pwm_mode {
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PWM_OFF = 0, /* disabled, deallocated */
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PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
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PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
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PWM_VARFREQ = 3, /* individually configurable high/low periods */
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PWM_SOFT = 4 /* software generated */
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};
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struct io_pwm_set_mode {
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enum io_pwm_mode mode;
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};
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/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
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* from 10ns (value = 0) to 81920ns (value = 8191)
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* (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
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* 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
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* cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
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*/
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#define IO_PWM_SET_PERIOD 0x21
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struct io_pwm_set_period {
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unsigned int lo; /* 0..8191 */
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unsigned int hi; /* 0..8191 */
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};
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/* Only for modes PWM_STANDARD and PWM_FAST.
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* For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
|
||||
* 0 (value = 0) to 255/256 (value = 255).
|
||||
* For PWM_FAST, set duty cycle of PWM output signal from
|
||||
* 0% (value = 0) to 100% (value = 255). Output signal in this mode
|
||||
* is a 10ns pulse surrounded by a high or low level depending on duty
|
||||
* cycle (except for 0% and 100% which result in a constant output).
|
||||
* Resulting output frequency varies from 50 MHz at 50% duty cycle,
|
||||
* down to 390 kHz at min/max duty cycle.
|
||||
*/
|
||||
#define IO_PWM_SET_DUTY 0x22
|
||||
|
||||
struct io_pwm_set_duty {
|
||||
int duty; /* 0..255 */
|
||||
};
|
||||
|
||||
/* Returns information about the latest PWM pulse.
|
||||
* lo: Length of the latest low period, in units of 10ns.
|
||||
* hi: Length of the latest high period, in units of 10ns.
|
||||
* cnt: Time since last detected edge, in units of 10ns.
|
||||
*
|
||||
* The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
|
||||
*
|
||||
* NOTE: All PWM devices is connected to the same input source.
|
||||
*/
|
||||
#define IO_PWM_GET_PERIOD 0x23
|
||||
|
||||
struct io_pwm_get_period {
|
||||
unsigned int lo;
|
||||
unsigned int hi;
|
||||
unsigned int cnt;
|
||||
};
|
||||
|
||||
/* Sets the input source for the PWM input. For the src value see the
|
||||
* register description for gio:rw_pwm_in_cfg.
|
||||
*
|
||||
* NOTE: All PWM devices is connected to the same input source.
|
||||
*/
|
||||
#define IO_PWM_SET_INPUT_SRC 0x24
|
||||
struct io_pwm_set_input_src {
|
||||
unsigned int src; /* 0..7 */
|
||||
};
|
||||
|
||||
/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
|
||||
#define IO_PPWM_SET_DUTY 0x25
|
||||
|
||||
struct io_ppwm_set_duty {
|
||||
int duty; /* 0..255 */
|
||||
};
|
||||
|
||||
/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
|
||||
* PWM capable gpio pins:
|
||||
*/
|
||||
#define IO_PWMCLK_SETGET_CONFIG 0x26
|
||||
struct gpio_pwmclk_conf {
|
||||
unsigned int gpiopin; /* The pin number based on the opened device */
|
||||
unsigned int baseclk; /* The base clock to use, or sw will select one close*/
|
||||
unsigned int low; /* The number of low periods of the baseclk */
|
||||
unsigned int high; /* The number of high periods of the baseclk */
|
||||
};
|
||||
|
||||
/* Examples:
|
||||
* To get a symmetric 12 MHz clock without knowing anything about the hardware:
|
||||
* baseclk = 12000000, low = 0, high = 0
|
||||
* To just get info of current setting:
|
||||
* baseclk = 0, low = 0, high = 0, the values will be updated by driver.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue