drm/amdkfd: Add address watch operation to debugger
The address watch operation gives the ability to specify watch points which will generate a shader breakpoint, based on a specified single address or range of addresses. There is support for read/write/any access modes. Signed-off-by: Yair Shachar <yair.shachar@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Yair Shachar
Oded Gabbay
parent
788bf83db3
commit
e2e9afc4a3
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@ -236,6 +236,278 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev)
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return status;
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}
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static void dbgdev_address_watch_set_registers(
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const struct dbg_address_watch_info *adw_info,
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union TCP_WATCH_ADDR_H_BITS *addrHi,
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union TCP_WATCH_ADDR_L_BITS *addrLo,
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union TCP_WATCH_CNTL_BITS *cntl,
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unsigned int index, unsigned int vmid)
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{
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union ULARGE_INTEGER addr;
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BUG_ON(!adw_info || !addrHi || !addrLo || !cntl);
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addr.quad_part = 0;
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addrHi->u32All = 0;
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addrLo->u32All = 0;
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cntl->u32All = 0;
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if (adw_info->watch_mask != NULL)
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cntl->bitfields.mask =
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(uint32_t) (adw_info->watch_mask[index] &
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK);
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else
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cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
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addr.quad_part = (unsigned long long) adw_info->watch_address[index];
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addrHi->bitfields.addr = addr.u.high_part &
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ADDRESS_WATCH_REG_ADDHIGH_MASK;
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addrLo->bitfields.addr =
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(addr.u.low_part >> ADDRESS_WATCH_REG_ADDLOW_SHIFT);
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cntl->bitfields.mode = adw_info->watch_mode[index];
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cntl->bitfields.vmid = (uint32_t) vmid;
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/* for now assume it is an ATC address */
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cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
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pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "set reg add high :",
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addrHi->bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "set reg add low :",
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addrLo->bitfields.addr);
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}
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static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info)
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{
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union TCP_WATCH_ADDR_H_BITS addrHi;
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union TCP_WATCH_ADDR_L_BITS addrLo;
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union TCP_WATCH_CNTL_BITS cntl;
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struct kfd_process_device *pdd;
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unsigned int i;
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BUG_ON(!dbgdev || !dbgdev->dev || !adw_info);
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/* taking the vmid for that process on the safe way using pdd */
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pdd = kfd_get_process_device_data(dbgdev->dev,
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adw_info->process);
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if (!pdd) {
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pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n");
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return -EFAULT;
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}
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addrHi.u32All = 0;
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addrLo.u32All = 0;
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cntl.u32All = 0;
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if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
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(adw_info->num_watch_points == 0)) {
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pr_err("amdkfd: num_watch_points is invalid\n");
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return -EINVAL;
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}
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if ((adw_info->watch_mode == NULL) ||
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(adw_info->watch_address == NULL)) {
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pr_err("amdkfd: adw_info fields are not valid\n");
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return -EINVAL;
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}
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for (i = 0 ; i < adw_info->num_watch_points ; i++) {
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dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo,
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&cntl, i, pdd->qpd.vmid);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t%20s %08x\n", "register index :", i);
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pr_debug("\t\t%20s %08x\n", "vmid is :", pdd->qpd.vmid);
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pr_debug("\t\t%20s %08x\n", "Address Low is :",
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addrLo.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Control Mask is :",
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cntl.bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "Control Mode is :",
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cntl.bitfields.mode);
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pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
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cntl.bitfields.vmid);
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pr_debug("\t\t%20s %08x\n", "Control atc is :",
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cntl.bitfields.atc);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pdd->dev->kfd2kgd->address_watch_execute(
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dbgdev->dev->kgd,
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i,
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cntl.u32All,
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addrHi.u32All,
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addrLo.u32All);
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}
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return 0;
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}
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static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info)
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{
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struct pm4__set_config_reg *packets_vec;
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union TCP_WATCH_ADDR_H_BITS addrHi;
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union TCP_WATCH_ADDR_L_BITS addrLo;
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union TCP_WATCH_CNTL_BITS cntl;
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struct kfd_mem_obj *mem_obj;
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unsigned int aw_reg_add_dword;
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uint32_t *packet_buff_uint;
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unsigned int i;
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int status;
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size_t ib_size = sizeof(struct pm4__set_config_reg) * 4;
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/* we do not control the vmid in DIQ mode, just a place holder */
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unsigned int vmid = 0;
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BUG_ON(!dbgdev || !dbgdev->dev || !adw_info);
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addrHi.u32All = 0;
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addrLo.u32All = 0;
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cntl.u32All = 0;
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if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
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(adw_info->num_watch_points == 0)) {
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pr_err("amdkfd: num_watch_points is invalid\n");
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return -EINVAL;
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}
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if ((NULL == adw_info->watch_mode) ||
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(NULL == adw_info->watch_address)) {
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pr_err("amdkfd: adw_info fields are not valid\n");
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return -EINVAL;
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}
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status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
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if (status != 0) {
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pr_err("amdkfd: Failed to allocate GART memory\n");
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return status;
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}
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packet_buff_uint = mem_obj->cpu_ptr;
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memset(packet_buff_uint, 0, ib_size);
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packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint);
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packets_vec[0].header.count = 1;
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packets_vec[0].header.opcode = IT_SET_CONFIG_REG;
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packets_vec[0].header.type = PM4_TYPE_3;
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packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
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packets_vec[0].bitfields2.insert_vmid = 1;
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packets_vec[1].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[1].bitfields2.insert_vmid = 0;
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packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[2].bitfields2.insert_vmid = 0;
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packets_vec[3].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
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packets_vec[3].bitfields2.insert_vmid = 1;
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for (i = 0; i < adw_info->num_watch_points; i++) {
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dbgdev_address_watch_set_registers(adw_info,
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&addrHi,
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&addrLo,
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&cntl,
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i,
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vmid);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t%20s %08x\n", "register index :", i);
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pr_debug("\t\t%20s %08x\n", "vmid is :", vmid);
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pr_debug("\t\t%20s %p\n", "Add ptr is :",
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adw_info->watch_address);
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pr_debug("\t\t%20s %08llx\n", "Add is :",
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adw_info->watch_address[i]);
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pr_debug("\t\t%20s %08x\n", "Address Low is :",
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addrLo.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Address high is :",
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addrHi.bitfields.addr);
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pr_debug("\t\t%20s %08x\n", "Control Mask is :",
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cntl.bitfields.mask);
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pr_debug("\t\t%20s %08x\n", "Control Mode is :",
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cntl.bitfields.mode);
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pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
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cntl.bitfields.vmid);
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pr_debug("\t\t%20s %08x\n", "Control atc is :",
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cntl.bitfields.atc);
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pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
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aw_reg_add_dword =
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dbgdev->dev->kfd2kgd->address_watch_get_offset(
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dbgdev->dev->kgd,
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i,
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ADDRESS_WATCH_REG_CNTL);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[0].bitfields2.reg_offset =
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aw_reg_add_dword - CONFIG_REG_BASE;
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packets_vec[0].reg_data[0] = cntl.u32All;
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aw_reg_add_dword =
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dbgdev->dev->kfd2kgd->address_watch_get_offset(
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dbgdev->dev->kgd,
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i,
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ADDRESS_WATCH_REG_ADDR_HI);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[1].bitfields2.reg_offset =
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aw_reg_add_dword - CONFIG_REG_BASE;
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packets_vec[1].reg_data[0] = addrHi.u32All;
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aw_reg_add_dword =
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dbgdev->dev->kfd2kgd->address_watch_get_offset(
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dbgdev->dev->kgd,
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i,
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ADDRESS_WATCH_REG_ADDR_LO);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[2].bitfields2.reg_offset =
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aw_reg_add_dword - CONFIG_REG_BASE;
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packets_vec[2].reg_data[0] = addrLo.u32All;
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/* enable watch flag if address is not zero*/
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if (adw_info->watch_address[i] > 0)
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cntl.bitfields.valid = 1;
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else
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cntl.bitfields.valid = 0;
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aw_reg_add_dword =
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dbgdev->dev->kfd2kgd->address_watch_get_offset(
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dbgdev->dev->kgd,
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i,
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ADDRESS_WATCH_REG_CNTL);
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aw_reg_add_dword /= sizeof(uint32_t);
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packets_vec[3].bitfields2.reg_offset =
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aw_reg_add_dword - CONFIG_REG_BASE;
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packets_vec[3].reg_data[0] = cntl.u32All;
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status = dbgdev_diq_submit_ib(
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dbgdev,
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adw_info->process->pasid,
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mem_obj->gpu_addr,
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packet_buff_uint,
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ib_size);
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if (status != 0) {
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pr_err("amdkfd: Failed to submit IB to DIQ\n");
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break;
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}
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}
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kfd_gtt_sa_free(dbgdev->dev, mem_obj);
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return status;
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}
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static int dbgdev_wave_control_set_registers(
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struct dbg_wave_control_info *wac_info,
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union SQ_CMD_BITS *in_reg_sq_cmd,
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@ -535,12 +807,14 @@ void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
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pdbgdev->dbgdev_register = dbgdev_register_nodiq;
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pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq;
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pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq;
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pdbgdev->dbgdev_address_watch = dbgdev_address_watch_nodiq;
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break;
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case DBGDEV_TYPE_DIQ:
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default:
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pdbgdev->dbgdev_register = dbgdev_register_diq;
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pdbgdev->dbgdev_unregister = dbgdev_unregister_diq;
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pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq;
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pdbgdev->dbgdev_address_watch = dbgdev_address_watch_diq;
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break;
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}
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@ -149,3 +149,20 @@ long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
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return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info);
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}
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long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
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struct dbg_address_watch_info *adw_info)
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{
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BUG_ON(!pmgr || !pmgr->dbgdev || !adw_info);
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/* Is the requests coming from the already registered process? */
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if (pmgr->pasid != adw_info->process->pasid) {
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pr_debug("H/W debugger support was not registered for requester pasid %d\n",
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adw_info->process->pasid);
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return -EINVAL;
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}
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return (long) pmgr->dbgdev->dbgdev_address_watch(pmgr->dbgdev,
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adw_info);
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}
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@ -268,6 +268,8 @@ struct kfd_dbgdev {
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/* virtualized function pointers to device dbg */
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int (*dbgdev_register)(struct kfd_dbgdev *dbgdev);
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int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev);
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int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info);
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int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev,
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struct dbg_wave_control_info *wac_info);
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@ -287,4 +289,6 @@ long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
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long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
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long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
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struct dbg_wave_control_info *wac_info);
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long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
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struct dbg_address_watch_info *adw_info);
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#endif /* KFD_DBGMGR_H_ */
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