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gma500: CodingStyle pass 

Start the style cleanup

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox 2011-07-05 15:36:19 +01:00 committed by Greg Kroah-Hartman
parent 2cf10d23df
commit e2e88603c8
15 changed files with 1110 additions and 1094 deletions
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26
drivers/staging/gma500/mrst.h
View File

@ -25,7 +25,7 @@ struct mrst_vbt {
u8 size; u8 size;
u8 checksum; u8 checksum;
void *mrst_gct; void *mrst_gct;
} __attribute__ ((packed)); } __packed;
struct mrst_timing_info { struct mrst_timing_info {
u16 pixel_clock; u16 pixel_clock;
@ -58,7 +58,7 @@ struct mrst_timing_info {
u8 stereo:1; u8 stereo:1;
u8 unknown6:1; u8 unknown6:1;
u8 interlaced:1; u8 interlaced:1;
} __attribute__((packed)); } __packed;
struct gct_r10_timing_info { struct gct_r10_timing_info {
u16 pixel_clock; u16 pixel_clock;
@ -82,7 +82,7 @@ struct gct_r10_timing_info {
u16 vsync_pulse_width_hi:2; u16 vsync_pulse_width_hi:2;
u16 vsync_positive:1; u16 vsync_positive:1;
u16 rsvd_2:3; u16 rsvd_2:3;
} __attribute__((packed)); } __packed;
struct mrst_panel_descriptor_v1 { struct mrst_panel_descriptor_v1 {
u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
@ -111,7 +111,7 @@ struct mrst_panel_descriptor_v1 {
/* Bit 6, Reserved, 2 bits, 00b */ /* Bit 6, Reserved, 2 bits, 00b */
/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
/* Bit 14, Reserved, 2 bits, 00b */ /* Bit 14, Reserved, 2 bits, 00b */
} __attribute__ ((packed)); } __packed;
struct mrst_panel_descriptor_v2 { struct mrst_panel_descriptor_v2 {
u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
@ -141,10 +141,10 @@ struct mrst_panel_descriptor_v2 {
/* Bit 6, Reserved, 2 bits, 00b */ /* Bit 6, Reserved, 2 bits, 00b */
/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
/* Bit 14, Reserved, 2 bits, 00b */ /* Bit 14, Reserved, 2 bits, 00b */
} __attribute__ ((packed)); } __packed;
union mrst_panel_rx { union mrst_panel_rx {
struct{ struct {
u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
@ -159,10 +159,10 @@ union mrst_panel_rx {
u16 Rsvd:5;/*5 bits,00000b */ u16 Rsvd:5;/*5 bits,00000b */
} panelrx; } panelrx;
u16 panel_receiver; u16 panel_receiver;
} __attribute__ ((packed)); } __packed;
struct mrst_gct_v1 { struct mrst_gct_v1 {
union{ /*8 bits,Defined as follows: */ union { /*8 bits,Defined as follows: */
struct { struct {
u8 PanelType:4; /*4 bits, Bit field for panels*/ u8 PanelType:4; /*4 bits, Bit field for panels*/
/* 0 - 3: 0 = LVDS, 1 = MIPI*/ /* 0 - 3: 0 = LVDS, 1 = MIPI*/
@ -176,10 +176,10 @@ struct mrst_gct_v1 {
}; };
struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
union mrst_panel_rx panelrx[4]; /* panel receivers*/ union mrst_panel_rx panelrx[4]; /* panel receivers*/
} __attribute__ ((packed)); } __packed;
struct mrst_gct_v2 { struct mrst_gct_v2 {
union{ /*8 bits,Defined as follows: */ union { /*8 bits,Defined as follows: */
struct { struct {
u8 PanelType:4; /*4 bits, Bit field for panels*/ u8 PanelType:4; /*4 bits, Bit field for panels*/
/* 0 - 3: 0 = LVDS, 1 = MIPI*/ /* 0 - 3: 0 = LVDS, 1 = MIPI*/
@ -193,7 +193,7 @@ struct mrst_gct_v2 {
}; };
struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
union mrst_panel_rx panelrx[4]; /* panel receivers*/ union mrst_panel_rx panelrx[4]; /* panel receivers*/
} __attribute__ ((packed)); } __packed;
struct mrst_gct_data { struct mrst_gct_data {
u8 bpi; /* boot panel index, number of panel used during boot */ u8 bpi; /* boot panel index, number of panel used during boot */
@ -205,13 +205,13 @@ struct mrst_gct_data {
u32 PP_Cycle_Delay; u32 PP_Cycle_Delay;
u16 Panel_Backlight_Inverter_Descriptor; u16 Panel_Backlight_Inverter_Descriptor;
u16 Panel_MIPI_Display_Descriptor; u16 Panel_MIPI_Display_Descriptor;
} __attribute__ ((packed)); } __packed;
#define MODE_SETTING_IN_CRTC 0x1 #define MODE_SETTING_IN_CRTC 0x1
#define MODE_SETTING_IN_ENCODER 0x2 #define MODE_SETTING_IN_ENCODER 0x2
#define MODE_SETTING_ON_GOING 0x3 #define MODE_SETTING_ON_GOING 0x3
#define MODE_SETTING_IN_DSR 0x4 #define MODE_SETTING_IN_DSR 0x4
#define MODE_SETTING_ENCODER_DONE 0x8 #define MODE_SETTING_ENCODER_DONE 0x8
#define GCT_R10_HEADER_SIZE 16 #define GCT_R10_HEADER_SIZE 16
#define GCT_R10_DISPLAY_DESC_SIZE 28 #define GCT_R10_DISPLAY_DESC_SIZE 28

9
drivers/staging/gma500/psb_2d.c
View File

@ -47,7 +47,7 @@ void psb_spank(struct drm_psb_private *dev_priv)
_PSB_CS_RESET_TA_RESET | _PSB_CS_RESET_USE_RESET | _PSB_CS_RESET_TA_RESET | _PSB_CS_RESET_USE_RESET |
_PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET | _PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET |
_PSB_CS_RESET_TWOD_RESET, PSB_CR_SOFT_RESET); _PSB_CS_RESET_TWOD_RESET, PSB_CR_SOFT_RESET);
(void) PSB_RSGX32(PSB_CR_SOFT_RESET); PSB_RSGX32(PSB_CR_SOFT_RESET);
msleep(1); msleep(1);
@ -71,7 +71,7 @@ static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF); uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
unsigned long t = jiffies + HZ; unsigned long t = jiffies + HZ;
while(avail < size) { while (avail < size) {
avail = PSB_RSGX32(PSB_CR_2D_SOCIF); avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
if (time_after(jiffies, t)) { if (time_after(jiffies, t)) {
psb_spank(dev_priv); psb_spank(dev_priv);
@ -99,9 +99,10 @@ int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
return ret; return ret;
submit_size <<= 2; submit_size <<= 2;
for (i = 0; i < submit_size; i += 4) {
for (i = 0; i < submit_size; i += 4)
PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i); PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i);
}
(void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4); (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4);
} }
return 0; return 0;

13
drivers/staging/gma500/psb_drv.c
View File

@ -47,7 +47,7 @@ module_param_named(no_fb, drm_psb_no_fb, int, 0600);
module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600); module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
static struct pci_device_id pciidlist[] = { static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 }, { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 }, { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
{ 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
@ -185,8 +185,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
if (dev_priv->iLVDS_enable) { if (dev_priv->iLVDS_enable) {
dev_priv->is_lvds_on = true; dev_priv->is_lvds_on = true;
dev_priv->is_mipi_on = false; dev_priv->is_mipi_on = false;
} } else {
else {
dev_priv->is_mipi_on = true; dev_priv->is_mipi_on = true;
dev_priv->is_lvds_on = false; dev_priv->is_lvds_on = false;
} }
@ -196,7 +195,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
pci_write_config_dword(pci_root, 0xD0, FB_REG09); pci_write_config_dword(pci_root, 0xD0, FB_REG09);
pci_read_config_dword(pci_root, 0xD4, &fuse_value); pci_read_config_dword(pci_root, 0xD4, &fuse_value);
DRM_INFO("SKU values is 0x%x. \n", fuse_value); DRM_INFO("SKU values is 0x%x.\n", fuse_value);
fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT; fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
dev_priv->fuse_reg_value = fuse_value; dev_priv->fuse_reg_value = fuse_value;
@ -220,7 +219,7 @@ void mrst_get_fuse_settings(struct drm_device *dev)
pci_dev_put(pci_root); pci_dev_put(pci_root);
} }
void mid_get_pci_revID (struct drm_psb_private *dev_priv) void mid_get_pci_revID(struct drm_psb_private *dev_priv)
{ {
uint32_t platform_rev_id = 0; uint32_t platform_rev_id = 0;
struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0)); struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
@ -455,7 +454,6 @@ static int psb_do_init(struct drm_device *dev)
/* mmu_gatt ?? */ /* mmu_gatt ?? */
PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
return 0; return 0;
out_err: out_err:
psb_do_takedown(dev); psb_do_takedown(dev);
@ -1335,7 +1333,6 @@ static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
dev_priv->rpm_enabled = 1; dev_priv->rpm_enabled = 1;
} }
return drm_ioctl(filp, cmd, arg); return drm_ioctl(filp, cmd, arg);
/* FIXME: do we need to wrap the other side of this */ /* FIXME: do we need to wrap the other side of this */
} }
@ -1367,7 +1364,7 @@ static struct vm_operations_struct psb_gem_vm_ops = {
static struct drm_driver driver = { static struct drm_driver driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM , DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
.load = psb_driver_load, .load = psb_driver_load,
.unload = psb_driver_unload, .unload = psb_driver_unload,

47
drivers/staging/gma500/psb_drv.h
View File

@ -25,6 +25,7 @@
#include <drm/drmP.h> #include <drm/drmP.h>
#include "drm_global.h" #include "drm_global.h"
#include "gem_glue.h"
#include "psb_drm.h" #include "psb_drm.h"
#include "psb_reg.h" #include "psb_reg.h"
#include "psb_intel_drv.h" #include "psb_intel_drv.h"
@ -132,8 +133,12 @@ enum {
#define _LNC_IRQ_TOPAZ_FLAG (1<<20) #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
/* This flag includes all the display IRQ bits excepts the vblank irqs. */ /* This flag includes all the display IRQ bits excepts the vblank irqs. */
#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \ #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
_PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG) _MDFLD_PIPEB_EVENT_FLAG | \
_PSB_PIPEA_EVENT_FLAG | \
_PSB_VSYNC_PIPEA_FLAG | \
_MDFLD_MIPIA_FLAG | \
_MDFLD_MIPIC_FLAG)
#define PSB_INT_IDENTITY_R 0x20A4 #define PSB_INT_IDENTITY_R 0x20A4
#define PSB_INT_MASK_R 0x20A8 #define PSB_INT_MASK_R 0x20A8
#define PSB_INT_ENABLE_R 0x20A0 #define PSB_INT_ENABLE_R 0x20A0
@ -480,7 +485,7 @@ struct drm_psb_private {
uint32_t blc_adj1; uint32_t blc_adj1;
uint32_t blc_adj2; uint32_t blc_adj2;
void * fbdev; void *fbdev;
}; };
@ -550,7 +555,7 @@ extern void psb_irq_turn_on_dpst(struct drm_device *dev);
extern void psb_irq_turn_off_dpst(struct drm_device *dev); extern void psb_irq_turn_off_dpst(struct drm_device *dev);
extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence); extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
extern int psb_enable_vblank(struct drm_device *dev, int crtc); extern int psb_enable_vblank(struct drm_device *dev, int crtc);
extern void psb_disable_vblank(struct drm_device *dev, int crtc); extern void psb_disable_vblank(struct drm_device *dev, int crtc);
@ -606,14 +611,14 @@ extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
/* modesetting */ /* modesetting */
extern void psb_modeset_init(struct drm_device *dev); extern void psb_modeset_init(struct drm_device *dev);
extern void psb_modeset_cleanup(struct drm_device *dev); extern void psb_modeset_cleanup(struct drm_device *dev);
extern int psb_fbdev_init(struct drm_device * dev); extern int psb_fbdev_init(struct drm_device *dev);
/* psb_bl.c */ /* psb_bl.c */
int psb_backlight_init(struct drm_device *dev); int psb_backlight_init(struct drm_device *dev);
void psb_backlight_exit(void); void psb_backlight_exit(void);
int psb_set_brightness(struct backlight_device *bd); int psb_set_brightness(struct backlight_device *bd);
int psb_get_brightness(struct backlight_device *bd); int psb_get_brightness(struct backlight_device *bd);
struct backlight_device * psb_get_backlight_device(void); struct backlight_device *psb_get_backlight_device(void);
/* mrst_crtc.c */ /* mrst_crtc.c */
extern const struct drm_crtc_helper_funcs mrst_helper_funcs; extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
@ -662,7 +667,6 @@ extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
extern int drm_psb_no_fb; extern int drm_psb_no_fb;
extern int drm_idle_check_interval; extern int drm_idle_check_interval;
/* /*
* Utilities * Utilities
*/ */
@ -671,36 +675,36 @@ static inline u32 MRST_MSG_READ32(uint port, uint offset)
{ {
int mcr = (0xD0<<24) | (port << 16) | (offset << 8); int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
uint32_t ret_val = 0; uint32_t ret_val = 0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword (pci_root, 0xD0, mcr); pci_write_config_dword(pci_root, 0xD0, mcr);
pci_read_config_dword (pci_root, 0xD4, &ret_val); pci_read_config_dword(pci_root, 0xD4, &ret_val);
pci_dev_put(pci_root); pci_dev_put(pci_root);
return ret_val; return ret_val;
} }
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value) static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
{ {
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword (pci_root, 0xD4, value); pci_write_config_dword(pci_root, 0xD4, value);
pci_write_config_dword (pci_root, 0xD0, mcr); pci_write_config_dword(pci_root, 0xD0, mcr);
pci_dev_put(pci_root); pci_dev_put(pci_root);
} }
static inline u32 MDFLD_MSG_READ32(uint port, uint offset) static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
{ {
int mcr = (0x10<<24) | (port << 16) | (offset << 8); int mcr = (0x10<<24) | (port << 16) | (offset << 8);
uint32_t ret_val = 0; uint32_t ret_val = 0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword (pci_root, 0xD0, mcr); pci_write_config_dword(pci_root, 0xD0, mcr);
pci_read_config_dword (pci_root, 0xD4, &ret_val); pci_read_config_dword(pci_root, 0xD4, &ret_val);
pci_dev_put(pci_root); pci_dev_put(pci_root);
return ret_val; return ret_val;
} }
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value) static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
{ {
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0); struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
pci_write_config_dword (pci_root, 0xD4, value); pci_write_config_dword(pci_root, 0xD4, value);
pci_write_config_dword (pci_root, 0xD0, mcr); pci_write_config_dword(pci_root, 0xD0, mcr);
pci_dev_put(pci_root); pci_dev_put(pci_root);
} }
@ -747,9 +751,10 @@ static inline void REGISTER_WRITE8(struct drm_device *dev,
#define PSB_RSGX32(_offs) \ #define PSB_RSGX32(_offs) \
({ \ ({ \
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \ printk(KERN_ERR \
"access sgx when it's off!! (READ) %s, %d\n", \
__FILE__, __LINE__); \ __FILE__, __LINE__); \
mdelay(1000); \ melay(1000); \
} \ } \
ioread32(dev_priv->sgx_reg + (_offs)); \ ioread32(dev_priv->sgx_reg + (_offs)); \
}) })

31
drivers/staging/gma500/psb_fb.c
View File

@ -244,9 +244,11 @@ static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
fb_screen_base = (char *)info->screen_base; fb_screen_base = (char *)info->screen_base;
/* If this is a GEM object then info->screen_base is the virtual /*
kernel remapping of the object. FIXME: Review if this is * If this is a GEM object then info->screen_base is the virtual
suitable for our mmap work */ * kernel remapping of the object. FIXME: Review if this is
* suitable for our mmap work
*/
vma->vm_ops = &psbfb_vm_ops; vma->vm_ops = &psbfb_vm_ops;
vma->vm_private_data = (void *)psbfb; vma->vm_private_data = (void *)psbfb;
vma->vm_flags |= VM_RESERVED | VM_IO | vma->vm_flags |= VM_RESERVED | VM_IO |
@ -254,7 +256,8 @@ static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
return 0; return 0;
} }
static int psbfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) static int psbfb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{ {
struct psb_fbdev *fbdev = info->par; struct psb_fbdev *fbdev = info->par;
struct psb_framebuffer *psbfb = &fbdev->pfb; struct psb_framebuffer *psbfb = &fbdev->pfb;
@ -384,7 +387,8 @@ static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size)
/* Begin by trying to use stolen memory backing */ /* Begin by trying to use stolen memory backing */
backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1); backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1);
if (backing) { if (backing) {
if (drm_gem_private_object_init(dev, &backing->gem, aligned_size) == 0) if (drm_gem_private_object_init(dev,
&backing->gem, aligned_size) == 0)
return backing; return backing;
psb_gtt_free_range(dev, backing); psb_gtt_free_range(dev, backing);
} }
@ -551,8 +555,10 @@ static struct drm_framebuffer *psb_user_framebuffer_create
struct gtt_range *r; struct gtt_range *r;
struct drm_gem_object *obj; struct drm_gem_object *obj;
/* Find the GEM object and thus the gtt range object that is /*
to back this space */ * Find the GEM object and thus the gtt range object that is
* to back this space
*/
obj = drm_gem_object_lookup(dev, filp, cmd->handle); obj = drm_gem_object_lookup(dev, filp, cmd->handle);
if (obj == NULL) if (obj == NULL)
return ERR_PTR(-ENOENT); return ERR_PTR(-ENOENT);
@ -718,11 +724,12 @@ static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
if (reset) if (reset)
/* /*
* Now force a sane response before we permit the DRM crc layer to * Now force a sane response before we permit the DRM CRTC
* do stupid things like blank the display. Instead we reset this * layer to do stupid things like blank the display. Instead
* framebuffer as if the user had forced a reset. We must do this * we reset this framebuffer as if the user had forced a reset.
* before the cleanup so that the DRM layer doesn't get a chance * We must do this before the cleanup so that the DRM layer
* to stick its oar in where it isn't wanted. * doesn't get a chance to stick its oar in where it isn't
* wanted.
*/ */
drm_fb_helper_restore_fbdev_mode(&fbdev->psb_fb_helper); drm_fb_helper_restore_fbdev_mode(&fbdev->psb_fb_helper);

5
drivers/staging/gma500/psb_gem.c
View File

@ -82,12 +82,13 @@ static int psb_gem_create_mmap_offset(struct drm_gem_object *obj)
map = list->map; map = list->map;
map->type = _DRM_GEM; map->type = _DRM_GEM;
map->size = obj->size; map->size = obj->size;
map->handle =obj; map->handle = obj;
list->file_offset_node = drm_mm_search_free(&mm->offset_manager, list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
obj->size / PAGE_SIZE, 0, 0); obj->size / PAGE_SIZE, 0, 0);
if (!list->file_offset_node) { if (!list->file_offset_node) {
dev_err(dev->dev, "failed to allocate offset for bo %d\n", obj->name); dev_err(dev->dev, "failed to allocate offset for bo %d\n",
obj->name);
ret = -ENOSPC; ret = -ENOSPC;
goto free_it; goto free_it;
} }

17
drivers/staging/gma500/psb_gtt.c
View File

@ -102,7 +102,6 @@ static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r)
} }
/* Make sure all the entries are set before we return */ /* Make sure all the entries are set before we return */
ioread32(gtt_slot - 1); ioread32(gtt_slot - 1);
return 0; return 0;
} }
@ -318,8 +317,8 @@ struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
* @dev: our DRM device * @dev: our DRM device
* @gt: a mapping created with psb_gtt_alloc_range * @gt: a mapping created with psb_gtt_alloc_range
* *
* Release a resource that was allocated with psb_gtt_alloc_range. If the object * Release a resource that was allocated with psb_gtt_alloc_range. If the
* has been pinned by mmap users we clean this up here currently. * object has been pinned by mmap users we clean this up here currently.
*/ */
void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt) void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
{ {
@ -409,11 +408,14 @@ int psb_gtt_init(struct drm_device *dev, int resume)
pg->mmu_gatt_start = 0xE0000000; pg->mmu_gatt_start = 0xE0000000;
pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE); pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT; gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE) >> PAGE_SHIFT; >> PAGE_SHIFT;
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
>> PAGE_SHIFT;
pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base); pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base - PAGE_SIZE; vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
- PAGE_SIZE;
stolen_size = vram_stolen_size; stolen_size = vram_stolen_size;
@ -439,7 +441,8 @@ int psb_gtt_init(struct drm_device *dev, int resume)
/* /*
* Map the GTT and the stolen memory area * Map the GTT and the stolen memory area
*/ */
dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT); dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start,
gtt_pages << PAGE_SHIFT);
if (!dev_priv->gtt_map) { if (!dev_priv->gtt_map) {
dev_err(dev->dev, "Failure to map gtt.\n"); dev_err(dev->dev, "Failure to map gtt.\n");
ret = -ENOMEM; ret = -ENOMEM;

8
drivers/staging/gma500/psb_intel_opregion.c
View File

@ -33,19 +33,19 @@ struct opregion_header {
u8 driver_ver[16]; u8 driver_ver[16];
u32 mboxes; u32 mboxes;
u8 reserved[164]; u8 reserved[164];
} __attribute__((packed)); } __packed;
struct opregion_apci { struct opregion_apci {
/*FIXME: add it later*/ /*FIXME: add it later*/
} __attribute__((packed)); } __packed;
struct opregion_swsci { struct opregion_swsci {
/*FIXME: add it later*/ /*FIXME: add it later*/
} __attribute__((packed)); } __packed;
struct opregion_acpi { struct opregion_acpi {
/*FIXME: add it later*/ /*FIXME: add it later*/
} __attribute__((packed)); } __packed;
int psb_intel_opregion_init(struct drm_device *dev) int psb_intel_opregion_init(struct drm_device *dev)
{ {

399
drivers/staging/gma500/psb_intel_reg.h
View File

@ -93,56 +93,55 @@
* - pipe enabled * - pipe enabled
* - LVDS/DVOB/DVOC on * - LVDS/DVOB/DVOC on
*/ */
# define PP_READY (1 << 30) #define PP_READY (1 << 30)
# define PP_SEQUENCE_NONE (0 << 28) #define PP_SEQUENCE_NONE (0 << 28)
# define PP_SEQUENCE_ON (1 << 28) #define PP_SEQUENCE_ON (1 << 28)
# define PP_SEQUENCE_OFF (2 << 28) #define PP_SEQUENCE_OFF (2 << 28)
# define PP_SEQUENCE_MASK 0x30000000 #define PP_SEQUENCE_MASK 0x30000000
#define PP_CONTROL 0x61204 #define PP_CONTROL 0x61204
# define POWER_TARGET_ON (1 << 0) #define POWER_TARGET_ON (1 << 0)
#define LVDSPP_ON 0x61208 #define LVDSPP_ON 0x61208
#define LVDSPP_OFF 0x6120c #define LVDSPP_OFF 0x6120c
#define PP_CYCLE 0x61210 #define PP_CYCLE 0x61210
#define PFIT_CONTROL 0x61230 #define PFIT_CONTROL 0x61230
# define PFIT_ENABLE (1 << 31) #define PFIT_ENABLE (1 << 31)
# define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_MASK (3 << 29)
# define PFIT_PIPE_SHIFT 29 #define PFIT_PIPE_SHIFT 29
# define PFIT_SCALING_MODE_PILLARBOX (1 << 27) #define PFIT_SCALING_MODE_PILLARBOX (1 << 27)
# define PFIT_SCALING_MODE_LETTERBOX (3 << 26) #define PFIT_SCALING_MODE_LETTERBOX (3 << 26)
# define VERT_INTERP_DISABLE (0 << 10) #define VERT_INTERP_DISABLE (0 << 10)
# define VERT_INTERP_BILINEAR (1 << 10) #define VERT_INTERP_BILINEAR (1 << 10)
# define VERT_INTERP_MASK (3 << 10) #define VERT_INTERP_MASK (3 << 10)
# define VERT_AUTO_SCALE (1 << 9) #define VERT_AUTO_SCALE (1 << 9)
# define HORIZ_INTERP_DISABLE (0 << 6) #define HORIZ_INTERP_DISABLE (0 << 6)
# define HORIZ_INTERP_BILINEAR (1 << 6) #define HORIZ_INTERP_BILINEAR (1 << 6)
# define HORIZ_INTERP_MASK (3 << 6) #define HORIZ_INTERP_MASK (3 << 6)
# define HORIZ_AUTO_SCALE (1 << 5) #define HORIZ_AUTO_SCALE (1 << 5)
# define PANEL_8TO6_DITHER_ENABLE (1 << 3) #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
#define PFIT_PGM_RATIOS 0x61234 #define PFIT_PGM_RATIOS 0x61234
# define PFIT_VERT_SCALE_MASK 0xfff00000 #define PFIT_VERT_SCALE_MASK 0xfff00000
# define PFIT_HORIZ_SCALE_MASK 0x0000fff0 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
#define PFIT_AUTO_RATIOS 0x61238 #define PFIT_AUTO_RATIOS 0x61238
#define DPLL_A 0x06014 #define DPLL_A 0x06014
#define DPLL_B 0x06018 #define DPLL_B 0x06018
# define DPLL_VCO_ENABLE (1 << 31) #define DPLL_VCO_ENABLE (1 << 31)
# define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_DVO_HIGH_SPEED (1 << 30)
# define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_SYNCLOCK_ENABLE (1 << 29)
# define DPLL_VGA_MODE_DIS (1 << 28) #define DPLL_VGA_MODE_DIS (1 << 28)
# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
# define DPLL_MODE_MASK (3 << 26) #define DPLL_MODE_MASK (3 << 26)
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
/* /*
* The i830 generation, in DAC/serial mode, defines p1 as two plus this * The i830 generation, in DAC/serial mode, defines p1 as two plus this
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
@ -152,35 +151,35 @@
* The i830 generation, in LVDS mode, defines P1 as the bit number set within * The i830 generation, in LVDS mode, defines P1 as the bit number set within
* this field (only one bit may be set). * this field (only one bit may be set).
*/ */
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required
* in DVO non-gang */ * in DVO non-gang */
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
# define PLL_REF_INPUT_DREFCLK (0 << 13) #define PLL_REF_INPUT_DREFCLK (0 << 13)
# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO
* TVCLKIN */ * TVCLKIN */
# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
# define PLL_REF_INPUT_MASK (3 << 13) #define PLL_REF_INPUT_MASK (3 << 13)
# define PLL_LOAD_PULSE_PHASE_SHIFT 9 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
/* /*
* Parallel to Serial Load Pulse phase selection. * Parallel to Serial Load Pulse phase selection.
* Selects the phase for the 10X DPLL clock for the PCIe * Selects the phase for the 10X DPLL clock for the PCIe
* digital display port. The range is 4 to 13; 10 or more * digital display port. The range is 4 to 13; 10 or more
* is just a flip delay. The default is 6 * is just a flip delay. The default is 6
*/ */
# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
/* /*
* SDVO multiplier for 945G/GM. Not used on 965. * SDVO multiplier for 945G/GM. Not used on 965.
* *
* DPLL_MD_UDI_MULTIPLIER_MASK * DPLL_MD_UDI_MULTIPLIER_MASK
*/ */
# define SDVO_MULTIPLIER_MASK 0x000000ff #define SDVO_MULTIPLIER_MASK 0x000000ff
# define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
# define SDVO_MULTIPLIER_SHIFT_VGA 0 #define SDVO_MULTIPLIER_SHIFT_VGA 0
/* /*
* PLL_MD * PLL_MD
@ -194,11 +193,11 @@
* *
* Value is pixels minus 1. Must be set to 1 pixel for SDVO. * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
*/ */
# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
# define DPLL_MD_UDI_DIVIDER_SHIFT 24 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
/* /*
* SDVO/UDI pixel multiplier. * SDVO/UDI pixel multiplier.
* *
@ -216,73 +215,72 @@
* This register field has values of multiplication factor minus 1, with * This register field has values of multiplication factor minus 1, with
* a maximum multiplier of 5 for SDVO. * a maximum multiplier of 5 for SDVO.
*/ */
# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
/* /*
* SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
* This best be set to the default value (3) or the CRT won't work. No, * This best be set to the default value (3) or the CRT won't work. No,
* I don't entirely understand what this does... * I don't entirely understand what this does...
*/ */
# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
#define DPLL_TEST 0x606c #define DPLL_TEST 0x606c
# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
# define DPLLB_TEST_N_BYPASS (1 << 19) #define DPLLB_TEST_N_BYPASS (1 << 19)
# define DPLLB_TEST_M_BYPASS (1 << 18) #define DPLLB_TEST_M_BYPASS (1 << 18)
# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
# define DPLLA_TEST_N_BYPASS (1 << 3) #define DPLLA_TEST_N_BYPASS (1 << 3)
# define DPLLA_TEST_M_BYPASS (1 << 2) #define DPLLA_TEST_M_BYPASS (1 << 2)
# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
#define ADPA 0x61100 #define ADPA 0x61100
#define ADPA_DAC_ENABLE (1<<31) #define ADPA_DAC_ENABLE (1 << 31)
#define ADPA_DAC_DISABLE 0 #define ADPA_DAC_DISABLE 0
#define ADPA_PIPE_SELECT_MASK (1<<30) #define ADPA_PIPE_SELECT_MASK (1 << 30)
#define ADPA_PIPE_A_SELECT 0 #define ADPA_PIPE_A_SELECT 0
#define ADPA_PIPE_B_SELECT (1<<30) #define ADPA_PIPE_B_SELECT (1 << 30)
#define ADPA_USE_VGA_HVPOLARITY (1<<15) #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
#define ADPA_SETS_HVPOLARITY 0 #define ADPA_SETS_HVPOLARITY 0
#define ADPA_VSYNC_CNTL_DISABLE (1<<11) #define ADPA_VSYNC_CNTL_DISABLE (1 << 11)
#define ADPA_VSYNC_CNTL_ENABLE 0 #define ADPA_VSYNC_CNTL_ENABLE 0
#define ADPA_HSYNC_CNTL_DISABLE (1<<10) #define ADPA_HSYNC_CNTL_DISABLE (1 << 10)
#define ADPA_HSYNC_CNTL_ENABLE 0 #define ADPA_HSYNC_CNTL_ENABLE 0
#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
#define ADPA_VSYNC_ACTIVE_LOW 0 #define ADPA_VSYNC_ACTIVE_LOW 0
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
#define ADPA_HSYNC_ACTIVE_LOW 0 #define ADPA_HSYNC_ACTIVE_LOW 0
#define FPA0 0x06040 #define FPA0 0x06040
#define FPA1 0x06044 #define FPA1 0x06044
#define FPB0 0x06048 #define FPB0 0x06048
#define FPB1 0x0604c #define FPB1 0x0604c
# define FP_N_DIV_MASK 0x003f0000 #define FP_N_DIV_MASK 0x003f0000
# define FP_N_DIV_SHIFT 16 #define FP_N_DIV_SHIFT 16
# define FP_M1_DIV_MASK 0x00003f00 #define FP_M1_DIV_MASK 0x00003f00
# define FP_M1_DIV_SHIFT 8 #define FP_M1_DIV_SHIFT 8
# define FP_M2_DIV_MASK 0x0000003f #define FP_M2_DIV_MASK 0x0000003f
# define FP_M2_DIV_SHIFT 0 #define FP_M2_DIV_SHIFT 0
#define PORT_HOTPLUG_EN 0x61110 #define PORT_HOTPLUG_EN 0x61110
# define SDVOB_HOTPLUG_INT_EN (1 << 26) #define SDVOB_HOTPLUG_INT_EN (1 << 26)
# define SDVOC_HOTPLUG_INT_EN (1 << 25) #define SDVOC_HOTPLUG_INT_EN (1 << 25)
# define TV_HOTPLUG_INT_EN (1 << 18) #define TV_HOTPLUG_INT_EN (1 << 18)
# define CRT_HOTPLUG_INT_EN (1 << 9) #define CRT_HOTPLUG_INT_EN (1 << 9)
# define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
#define PORT_HOTPLUG_STAT 0x61114 #define PORT_HOTPLUG_STAT 0x61114
# define CRT_HOTPLUG_INT_STATUS (1 << 11) #define CRT_HOTPLUG_INT_STATUS (1 << 11)
# define TV_HOTPLUG_INT_STATUS (1 << 10) #define TV_HOTPLUG_INT_STATUS (1 << 10)
# define CRT_HOTPLUG_MONITOR_MASK (3 << 8) #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
# define CRT_HOTPLUG_MONITOR_MONO (2 << 8) #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
# define CRT_HOTPLUG_MONITOR_NONE (0 << 8) #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
# define SDVOC_HOTPLUG_INT_STATUS (1 << 7) #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
# define SDVOB_HOTPLUG_INT_STATUS (1 << 6) #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
#define SDVOB 0x61140 #define SDVOB 0x61140
#define SDVOC 0x61160 #define SDVOC 0x61160
@ -290,6 +288,7 @@
#define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_PIPE_B_SELECT (1 << 30)
#define SDVO_STALL_SELECT (1 << 29) #define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26) #define SDVO_INTERRUPT_ENABLE (1 << 26)
/** /**
* 915G/GM SDVO pixel multiplier. * 915G/GM SDVO pixel multiplier.
* *
@ -321,71 +320,70 @@
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
* the DPLL semantics change when the LVDS is assigned to that pipe. * the DPLL semantics change when the LVDS is assigned to that pipe.
*/ */
# define LVDS_PORT_EN (1 << 31) #define LVDS_PORT_EN (1 << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */ /* Selects pipe B for LVDS data. Must be set on pre-965. */
# define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPEB_SELECT (1 << 30)
/* Turns on border drawing to allow centered display. */ /* Turns on border drawing to allow centered display. */
# define LVDS_BORDER_EN (1 << 15) #define LVDS_BORDER_EN (1 << 15)
/* /*
* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
* pixel. * pixel.
*/ */
# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
# define LVDS_A0A2_CLKA_POWER_UP (3 << 8) #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
/* /*
* Controls the A3 data pair, which contains the additional LSBs for 24 bit * Controls the A3 data pair, which contains the additional LSBs for 24 bit
* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
* on. * on.
*/ */
# define LVDS_A3_POWER_MASK (3 << 6) #define LVDS_A3_POWER_MASK (3 << 6)
# define LVDS_A3_POWER_DOWN (0 << 6) #define LVDS_A3_POWER_DOWN (0 << 6)
# define LVDS_A3_POWER_UP (3 << 6) #define LVDS_A3_POWER_UP (3 << 6)
/* /*
* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
* is set. * is set.
*/ */
# define LVDS_CLKB_POWER_MASK (3 << 4) #define LVDS_CLKB_POWER_MASK (3 << 4)
# define LVDS_CLKB_POWER_DOWN (0 << 4) #define LVDS_CLKB_POWER_DOWN (0 << 4)
# define LVDS_CLKB_POWER_UP (3 << 4) #define LVDS_CLKB_POWER_UP (3 << 4)
/* /*
* Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
* setting for whether we are in dual-channel mode. The B3 pair will * setting for whether we are in dual-channel mode. The B3 pair will
* additionally only be powered up when LVDS_A3_POWER_UP is set. * additionally only be powered up when LVDS_A3_POWER_UP is set.
*/ */
# define LVDS_B0B3_POWER_MASK (3 << 2) #define LVDS_B0B3_POWER_MASK (3 << 2)
# define LVDS_B0B3_POWER_DOWN (0 << 2) #define LVDS_B0B3_POWER_DOWN (0 << 2)
# define LVDS_B0B3_POWER_UP (3 << 2) #define LVDS_B0B3_POWER_UP (3 << 2)
#define PIPEACONF 0x70008 #define PIPEACONF 0x70008
#define PIPEACONF_ENABLE (1<<31) #define PIPEACONF_ENABLE (1 << 31)
#define PIPEACONF_DISABLE 0 #define PIPEACONF_DISABLE 0
#define PIPEACONF_DOUBLE_WIDE (1<<30) #define PIPEACONF_DOUBLE_WIDE (1 << 30)
#define PIPECONF_ACTIVE (1<<30) #define PIPECONF_ACTIVE (1 << 30)
#define I965_PIPECONF_ACTIVE (1<<30) #define I965_PIPECONF_ACTIVE (1 << 30)
#define PIPECONF_DSIPLL_LOCK (1<<29) #define PIPECONF_DSIPLL_LOCK (1 << 29)
#define PIPEACONF_SINGLE_WIDE 0 #define PIPEACONF_SINGLE_WIDE 0
#define PIPEACONF_PIPE_UNLOCKED 0 #define PIPEACONF_PIPE_UNLOCKED 0
#define PIPEACONF_DSR (1<<26) #define PIPEACONF_DSR (1 << 26)
#define PIPEACONF_PIPE_LOCKED (1<<25) #define PIPEACONF_PIPE_LOCKED (1 << 25)
#define PIPEACONF_PALETTE 0 #define PIPEACONF_PALETTE 0
#define PIPECONF_FORCE_BORDER (1<<25) #define PIPECONF_FORCE_BORDER (1 << 25)
#define PIPEACONF_GAMMA (1<<24) #define PIPEACONF_GAMMA (1 << 24)
#define PIPECONF_PROGRESSIVE (0 << 21) #define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
#define PIPECONF_PLANE_OFF (1<<19) #define PIPECONF_PLANE_OFF (1 << 19)
#define PIPECONF_CURSOR_OFF (1<<18) #define PIPECONF_CURSOR_OFF (1 << 18)
#define PIPEBCONF 0x71008 #define PIPEBCONF 0x71008
#define PIPEBCONF_ENABLE (1<<31) #define PIPEBCONF_ENABLE (1 << 31)
#define PIPEBCONF_DISABLE 0 #define PIPEBCONF_DISABLE 0
#define PIPEBCONF_DOUBLE_WIDE (1<<30) #define PIPEBCONF_DOUBLE_WIDE (1 << 30)
#define PIPEBCONF_DISABLE 0 #define PIPEBCONF_DISABLE 0
#define PIPEBCONF_GAMMA (1<<24) #define PIPEBCONF_GAMMA (1 << 24)
#define PIPEBCONF_PALETTE 0 #define PIPEBCONF_PALETTE 0
#define PIPECCONF 0x72008 #define PIPECCONF 0x72008
@ -397,39 +395,40 @@
#define PIPEASTAT 0x70024 #define PIPEASTAT 0x70024
#define PIPEBSTAT 0x71024 #define PIPEBSTAT 0x71024
#define PIPECSTAT 0x72024 #define PIPECSTAT 0x72024
#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
#define PIPE_VBLANK_CLEAR (1 << 1) #define PIPE_VBLANK_CLEAR (1 << 1)
#define PIPE_VBLANK_STATUS (1 << 1) #define PIPE_VBLANK_STATUS (1 << 1)
#define PIPE_TE_STATUS (1UL<<6) #define PIPE_TE_STATUS (1UL << 6)
#define PIPE_DPST_EVENT_STATUS (1UL<<7) #define PIPE_DPST_EVENT_STATUS (1UL << 7)
#define PIPE_VSYNC_CLEAR (1UL<<9) #define PIPE_VSYNC_CLEAR (1UL << 9)
#define PIPE_VSYNC_STATUS (1UL<<9) #define PIPE_VSYNC_STATUS (1UL << 9)
#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL<<10) #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)
#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL<<11) #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)
#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
#define PIPE_TE_ENABLE (1UL<<22) #define PIPE_TE_ENABLE (1UL << 22)
#define PIPE_DPST_EVENT_ENABLE (1UL<<23) #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
#define PIPE_VSYNC_ENABL (1UL<<25) #define PIPE_VSYNC_ENABL (1UL << 25)
#define PIPE_HDMI_AUDIO_UNDERRUN (1UL<<26) #define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)
#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL<<27) #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)
#define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | PIPE_HDMI_AUDIO_BUFFER_DONE) #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \
PIPE_HDMI_AUDIO_BUFFER_DONE)
#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
#define HISTOGRAM_INT_CONTROL 0x61268 #define HISTOGRAM_INT_CONTROL 0x61268
#define HISTOGRAM_BIN_DATA 0X61264 #define HISTOGRAM_BIN_DATA 0X61264
#define HISTOGRAM_LOGIC_CONTROL 0x61260 #define HISTOGRAM_LOGIC_CONTROL 0x61260
#define PWM_CONTROL_LOGIC 0x61250 #define PWM_CONTROL_LOGIC 0x61250
#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
#define HISTOGRAM_INTERRUPT_ENABLE (1UL<<31) #define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)
#define HISTOGRAM_LOGIC_ENABLE (1UL<<31) #define HISTOGRAM_LOGIC_ENABLE (1UL << 31)
#define PWM_LOGIC_ENABLE (1UL<<31) #define PWM_LOGIC_ENABLE (1UL << 31)
#define PWM_PHASEIN_ENABLE (1UL<<25) #define PWM_PHASEIN_ENABLE (1UL << 25)
#define PWM_PHASEIN_INT_ENABLE (1UL<<24) #define PWM_PHASEIN_INT_ENABLE (1UL << 24)
#define PWM_PHASEIN_VB_COUNT 0x00001f00 #define PWM_PHASEIN_VB_COUNT 0x00001f00
#define PWM_PHASEIN_INC 0x0000001f #define PWM_PHASEIN_INC 0x0000001f
#define HISTOGRAM_INT_CTRL_CLEAR (1UL<<30) #define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)
#define DPST_YUV_LUMA_MODE 0 #define DPST_YUV_LUMA_MODE 0
struct dpst_ie_histogram_control { struct dpst_ie_histogram_control {
@ -488,30 +487,30 @@ struct dpst_guardband {
#define DSPACNTR 0x70180 #define DSPACNTR 0x70180
#define DSPBCNTR 0x71180 #define DSPBCNTR 0x71180
#define DSPCCNTR 0x72180 #define DSPCCNTR 0x72180
#define DISPLAY_PLANE_ENABLE (1<<31) #define DISPLAY_PLANE_ENABLE (1 << 31)
#define DISPLAY_PLANE_DISABLE 0 #define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30) #define DISPPLANE_GAMMA_ENABLE (1 << 30)
#define DISPPLANE_GAMMA_DISABLE 0 #define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
#define DISPPLANE_8BPP (0x2<<26) #define DISPPLANE_8BPP (0x2 << 26)
#define DISPPLANE_15_16BPP (0x4<<26) #define DISPPLANE_15_16BPP (0x4 << 26)
#define DISPPLANE_16BPP (0x5<<26) #define DISPPLANE_16BPP (0x5 << 26)
#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)
#define DISPPLANE_32BPP (0x7<<26) #define DISPPLANE_32BPP (0x7 << 26)
#define DISPPLANE_STEREO_ENABLE (1<<25) #define DISPPLANE_STEREO_ENABLE (1 << 25)
#define DISPPLANE_STEREO_DISABLE 0 #define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_MASK (1<<24) #define DISPPLANE_SEL_PIPE_MASK (1 << 24)
#define DISPPLANE_SEL_PIPE_POS 24 #define DISPPLANE_SEL_PIPE_POS 24
#define DISPPLANE_SEL_PIPE_A 0 #define DISPPLANE_SEL_PIPE_A 0
#define DISPPLANE_SEL_PIPE_B (1<<24) #define DISPPLANE_SEL_PIPE_B (1 << 24)
#define DISPPLANE_SRC_KEY_ENABLE (1<<22) #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
#define DISPPLANE_SRC_KEY_DISABLE 0 #define DISPPLANE_SRC_KEY_DISABLE 0
#define DISPPLANE_LINE_DOUBLE (1<<20) #define DISPPLANE_LINE_DOUBLE (1 << 20)
#define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
/* plane B only */ /* plane B only */
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
#define DISPPLANE_ALPHA_TRANS_DISABLE 0 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
@ -553,9 +552,9 @@ struct dpst_guardband {
#define DSPCKEYMSK 0x72198 #define DSPCKEYMSK 0x72198
#define VGACNTRL 0x71400 #define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31) #define VGA_DISP_DISABLE (1 << 31)
# define VGA_2X_MODE (1 << 30) #define VGA_2X_MODE (1 << 30)
# define VGA_PIPE_B_SELECT (1 << 29) #define VGA_PIPE_B_SELECT (1 << 29)
/* /*
* Overlay registers * Overlay registers
@ -673,44 +672,44 @@ struct dpst_guardband {
* MEDFIELD HDMI registers * MEDFIELD HDMI registers
*/ */
#define HDMIPHYMISCCTL 0x61134 #define HDMIPHYMISCCTL 0x61134
# define HDMI_PHY_POWER_DOWN 0x7f #define HDMI_PHY_POWER_DOWN 0x7f
#define HDMIB_CONTROL 0x61140 #define HDMIB_CONTROL 0x61140
# define HDMIB_PORT_EN (1 << 31) #define HDMIB_PORT_EN (1 << 31)
# define HDMIB_PIPE_B_SELECT (1 << 30) #define HDMIB_PIPE_B_SELECT (1 << 30)
# define HDMIB_NULL_PACKET (1 << 9) #define HDMIB_NULL_PACKET (1 << 9)
#define HDMIB_HDCP_PORT (1 << 5) #define HDMIB_HDCP_PORT (1 << 5)
/* #define LVDS 0x61180 */ /* #define LVDS 0x61180 */
# define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) #define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)
# define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) #define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)
# define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) #define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)
#define MIPI 0x61190 #define MIPI 0x61190
#define MIPI_C 0x62190 #define MIPI_C 0x62190
# define MIPI_PORT_EN (1 << 31) #define MIPI_PORT_EN (1 << 31)
/* Turns on border drawing to allow centered display. */ /* Turns on border drawing to allow centered display. */
# define SEL_FLOPPED_HSTX (1 << 23) #define SEL_FLOPPED_HSTX (1 << 23)
# define PASS_FROM_SPHY_TO_AFE (1 << 16) #define PASS_FROM_SPHY_TO_AFE (1 << 16)
# define MIPI_BORDER_EN (1 << 15) #define MIPI_BORDER_EN (1 << 15)
# define MIPIA_3LANE_MIPIC_1LANE 0x1 #define MIPIA_3LANE_MIPIC_1LANE 0x1
# define MIPIA_2LANE_MIPIC_2LANE 0x2 #define MIPIA_2LANE_MIPIC_2LANE 0x2
# define TE_TRIGGER_DSI_PROTOCOL (1 << 2) #define TE_TRIGGER_DSI_PROTOCOL (1 << 2)
# define TE_TRIGGER_GPIO_PIN (1 << 3) #define TE_TRIGGER_GPIO_PIN (1 << 3)
#define MIPI_TE_COUNT 0x61194 #define MIPI_TE_COUNT 0x61194
/* #define PP_CONTROL 0x61204 */ /* #define PP_CONTROL 0x61204 */
# define POWER_DOWN_ON_RESET (1 << 1) #define POWER_DOWN_ON_RESET (1 << 1)
/* #define PFIT_CONTROL 0x61230 */ /* #define PFIT_CONTROL 0x61230 */
# define PFIT_PIPE_SELECT (3 << 29) #define PFIT_PIPE_SELECT (3 << 29)
# define PFIT_PIPE_SELECT_SHIFT (29) #define PFIT_PIPE_SELECT_SHIFT (29)
/* #define BLC_PWM_CTL 0x61254 */ /* #define BLC_PWM_CTL 0x61254 */
#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)
#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
/* #define PIPEACONF 0x70008 */ /* #define PIPEACONF 0x70008 */
#define PIPEACONF_PIPE_STATE (1<<30) #define PIPEACONF_PIPE_STATE (1 << 30)
/* #define DSPACNTR 0x70180 */ /* #define DSPACNTR 0x70180 */
#define MRST_DSPABASE 0x7019c #define MRST_DSPABASE 0x7019c
@ -725,6 +724,7 @@ struct dpst_guardband {
* MIPI IP registers * MIPI IP registers
*/ */
#define MIPIC_REG_OFFSET 0x800 #define MIPIC_REG_OFFSET 0x800
#define DEVICE_READY_REG 0xb000 #define DEVICE_READY_REG 0xb000
#define LP_OUTPUT_HOLD (1 << 16) #define LP_OUTPUT_HOLD (1 << 16)
#define EXIT_ULPS_DEV_READY 0x3 #define EXIT_ULPS_DEV_READY 0x3
@ -768,6 +768,7 @@ struct dpst_guardband {
#define FMT_DPI_POS 0x07 #define FMT_DPI_POS 0x07
#define FMT_DBI_POS 0x0A #define FMT_DBI_POS 0x0A
#define DBI_DATA_WIDTH_POS 0x0D #define DBI_DATA_WIDTH_POS 0x0D
/* DPI PIXEL FORMATS */ /* DPI PIXEL FORMATS */
#define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */
#define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */
@ -779,6 +780,7 @@ struct dpst_guardband {
#define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */
#define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */
#define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */
#define DBI_NOT_SUPPORTED 0x00 /* command mode #define DBI_NOT_SUPPORTED 0x00 /* command mode
* is not supported * is not supported
*/ */
@ -787,6 +789,7 @@ struct dpst_guardband {
#define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */
#define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */
#define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */
#define HS_TX_TIMEOUT_REG 0xb010 #define HS_TX_TIMEOUT_REG 0xb010
#define LP_RX_TIMEOUT_REG 0xb014 #define LP_RX_TIMEOUT_REG 0xb014
#define TURN_AROUND_TIMEOUT_REG 0xb018 #define TURN_AROUND_TIMEOUT_REG 0xb018
@ -824,7 +827,7 @@ struct dpst_guardband {
#define HS_GEN_DATA_REG 0xb068 #define HS_GEN_DATA_REG 0xb068
#define LP_GEN_CTRL_REG 0xb06C #define LP_GEN_CTRL_REG 0xb06C
#define HS_GEN_CTRL_REG 0xb070 #define HS_GEN_CTRL_REG 0xb070
#define DCS_CHANNEL_NUMBER_POS 0x06 #define DCS_CHANNEL_NUMBER_POS 0x6
#define MCS_COMMANDS_POS 0x8 #define MCS_COMMANDS_POS 0x8
#define WORD_COUNTS_POS 0x8 #define WORD_COUNTS_POS 0x8
#define MCS_PARAMETER_POS 0x10 #define MCS_PARAMETER_POS 0x10
@ -867,6 +870,7 @@ struct dpst_guardband {
#define MIPI_READ_DATA_RETURN_REG6 0xb130 #define MIPI_READ_DATA_RETURN_REG6 0xb130
#define MIPI_READ_DATA_RETURN_REG7 0xb134 #define MIPI_READ_DATA_RETURN_REG7 0xb134
#define MIPI_READ_DATA_VALID_REG 0xb138 #define MIPI_READ_DATA_VALID_REG 0xb138
/* DBI COMMANDS */ /* DBI COMMANDS */
#define soft_reset 0x01 #define soft_reset 0x01
/* /*
@ -968,7 +972,7 @@ No status bits are changed.
#define write_mem_start 0x2c #define write_mem_start 0x2c
/* /*
* This command transfers image data from the host processor to the * This command transfers image data from the host processor to the
* display module s frame memory starting at the pixel location specified * display modules frame memory starting at the pixel location specified
* by preceding set_column_address and set_page_address commands. * by preceding set_column_address and set_page_address commands.
*/ */
#define set_partial_area 0x30 #define set_partial_area 0x30
@ -1026,13 +1030,15 @@ No status bits are changed.
* Bits D[2:0] DBI Pixel Format Definition * Bits D[2:0] DBI Pixel Format Definition
* Bits D7 and D3 are not used. * Bits D7 and D3 are not used.
*/ */
#define DCS_PIXEL_FORMAT_3bbp 0x1 #define DCS_PIXEL_FORMAT_3bpp 0x1
#define DCS_PIXEL_FORMAT_8bbp 0x2 #define DCS_PIXEL_FORMAT_8bpp 0x2
#define DCS_PIXEL_FORMAT_12bbp 0x3 #define DCS_PIXEL_FORMAT_12bpp 0x3
#define DCS_PIXEL_FORMAT_16bbp 0x5 #define DCS_PIXEL_FORMAT_16bpp 0x5
#define DCS_PIXEL_FORMAT_18bbp 0x6 #define DCS_PIXEL_FORMAT_18bpp 0x6
#define DCS_PIXEL_FORMAT_24bbp 0x7 #define DCS_PIXEL_FORMAT_24bpp 0x7
#define write_mem_cont 0x3c #define write_mem_cont 0x3c
/* /*
* This command transfers image data from the host processor to the * This command transfers image data from the host processor to the
* display module's frame memory continuing from the pixel location * display module's frame memory continuing from the pixel location
@ -1117,7 +1123,8 @@ No status bits are changed.
* with Sync events * with Sync events
*/ */
#define BURST_MODE 0x03 /* Burst Mode */ #define BURST_MODE 0x03 /* Burst Mode */
#define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ /* Allocate at least #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */
/* Allocate at least
* 0x100 Byte with 32 * 0x100 Byte with 32
* byte alignment * byte alignment
*/ */
@ -1128,7 +1135,7 @@ No status bits are changed.
#define DBI_CB_TIME_OUT 0xFFFF #define DBI_CB_TIME_OUT 0xFFFF
#define GEN_FB_TIME_OUT 2000 #define GEN_FB_TIME_OUT 2000
#define ALIGNMENT_32BYTE_MASK (~((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)))
#define SKU_83 0x01 #define SKU_83 0x01
#define SKU_100 0x02 #define SKU_100 0x02
#define SKU_100L 0x04 #define SKU_100L 0x04

3
drivers/staging/gma500/psb_intel_sdvo.c
View File

@ -211,7 +211,8 @@ static void psb_intel_sdvo_write_cmd(struct psb_intel_output *psb_intel_output,
sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]);
i++) { i++) {
if (cmd == sdvo_cmd_names[i].cmd) { if (cmd == sdvo_cmd_names[i].cmd) {
printk(KERN_CONT "(%s)", sdvo_cmd_names[i].name); printk(KERN_CONT
"(%s)", sdvo_cmd_names[i].name);
break; break;
} }
} }

14
drivers/staging/gma500/psb_intel_sdvo_regs.h
View File

@ -51,7 +51,7 @@ struct psb_intel_sdvo_caps {
unsigned int stall_support:1; unsigned int stall_support:1;
unsigned int pad:1; unsigned int pad:1;
u16 output_flags; u16 output_flags;
} __attribute__ ((packed)); } __packed;
/** This matches the EDID DTD structure, more or less */ /** This matches the EDID DTD structure, more or less */
struct psb_intel_sdvo_dtd { struct psb_intel_sdvo_dtd {
@ -82,18 +82,18 @@ struct psb_intel_sdvo_dtd {
u8 v_sync_off_high; u8 v_sync_off_high;
u8 reserved; u8 reserved;
} part2; } part2;
} __attribute__ ((packed)); } __packed;
struct psb_intel_sdvo_pixel_clock_range { struct psb_intel_sdvo_pixel_clock_range {
u16 min; /**< pixel clock, in 10kHz units */ u16 min; /**< pixel clock, in 10kHz units */
u16 max; /**< pixel clock, in 10kHz units */ u16 max; /**< pixel clock, in 10kHz units */
} __attribute__ ((packed)); } __packed;
struct psb_intel_sdvo_preferred_input_timing_args { struct psb_intel_sdvo_preferred_input_timing_args {
u16 clock; u16 clock;
u16 width; u16 width;
u16 height; u16 height;
} __attribute__ ((packed)); } __packed;
/* I2C registers for SDVO */ /* I2C registers for SDVO */
#define SDVO_I2C_ARG_0 0x07 #define SDVO_I2C_ARG_0 0x07
@ -147,7 +147,7 @@ struct psb_intel_sdvo_get_trained_inputs_response {
unsigned int input0_trained:1; unsigned int input0_trained:1;
unsigned int input1_trained:1; unsigned int input1_trained:1;
unsigned int pad:6; unsigned int pad:6;
} __attribute__ ((packed)); } __packed;
/** Returns a struct psb_intel_sdvo_output_flags of active outputs. */ /** Returns a struct psb_intel_sdvo_output_flags of active outputs. */
#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
@ -201,7 +201,7 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
u16 interrupt_status; u16 interrupt_status;
unsigned int ambient_light_interrupt:1; unsigned int ambient_light_interrupt:1;
unsigned int pad:7; unsigned int pad:7;
} __attribute__ ((packed)); } __packed;
/** /**
* Selects which input is affected by future input commands. * Selects which input is affected by future input commands.
@ -214,7 +214,7 @@ struct psb_intel_sdvo_get_interrupt_event_source_response {
struct psb_intel_sdvo_set_target_input_args { struct psb_intel_sdvo_set_target_input_args {
unsigned int target_1:1; unsigned int target_1:1;
unsigned int pad:7; unsigned int pad:7;
} __attribute__ ((packed)); } __packed;
/** /**
* Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by * Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by

34
drivers/staging/gma500/psb_reg.h
View File

@ -135,7 +135,6 @@
#define PSB_CR_EVENT_KICK 0x0AC8 #define PSB_CR_EVENT_KICK 0x0AC8
#define _PSB_CE_KICK_NOW (1 << 0) #define _PSB_CE_KICK_NOW (1 << 0)
#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38 #define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
#define PSB_CR_BIF_CTRL 0x0C00 #define PSB_CR_BIF_CTRL 0x0C00
@ -160,11 +159,8 @@
#define _PSB_CBI_STAT_FAULT_HOST (1 << 9) #define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
#define PSB_CR_BIF_BANK0 0x0C78 #define PSB_CR_BIF_BANK0 0x0C78
#define PSB_CR_BIF_BANK1 0x0C7C #define PSB_CR_BIF_BANK1 0x0C7C
#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84 #define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88 #define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC #define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
@ -310,19 +306,19 @@
*Blit Rectangle (PSB_2D_BLIT_BH) *Blit Rectangle (PSB_2D_BLIT_BH)
*/ */
#define PSB_2D_ROT_MASK (3<<25) #define PSB_2D_ROT_MASK (3 << 25)
#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK) #define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
#define PSB_2D_ROT_NONE (0<<25) #define PSB_2D_ROT_NONE (0 << 25)
#define PSB_2D_ROT_90DEGS (1<<25) #define PSB_2D_ROT_90DEGS (1 << 25)
#define PSB_2D_ROT_180DEGS (2<<25) #define PSB_2D_ROT_180DEGS (2 << 25)
#define PSB_2D_ROT_270DEGS (3<<25) #define PSB_2D_ROT_270DEGS (3 << 25)
#define PSB_2D_COPYORDER_MASK (3<<23) #define PSB_2D_COPYORDER_MASK (3 << 23)
#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK) #define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
#define PSB_2D_COPYORDER_TL2BR (0<<23) #define PSB_2D_COPYORDER_TL2BR (0 << 23)
#define PSB_2D_COPYORDER_BR2TL (1<<23) #define PSB_2D_COPYORDER_BR2TL (1 << 23)
#define PSB_2D_COPYORDER_TR2BL (2<<23) #define PSB_2D_COPYORDER_TR2BL (2 << 23)
#define PSB_2D_COPYORDER_BL2TR (3<<23) #define PSB_2D_COPYORDER_BL2TR (3 << 23)
#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF) #define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
#define PSB_2D_DSTCK_DISABLE (0x00000000) #define PSB_2D_DSTCK_DISABLE (0x00000000)
@ -531,7 +527,6 @@
#define PSB_2D_ROP3_PAT (0xF0) #define PSB_2D_ROP3_PAT (0xF0)
#define PSB_2D_ROP3_DST (0xAA) #define PSB_2D_ROP3_DST (0xAA)
/* /*
* Sizes. * Sizes.
*/ */
@ -554,8 +549,7 @@
#define PSB_RETURN 2 #define PSB_RETURN 2
#define PSB_TA 3 #define PSB_TA 3
/* Power management */
/*Power management*/
#define PSB_PUNIT_PORT 0x04 #define PSB_PUNIT_PORT 0x04
#define PSB_OSPMBA 0x78 #define PSB_OSPMBA 0x78
#define PSB_APMBA 0x7a #define PSB_APMBA 0x7a
@ -572,7 +566,7 @@
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000 #define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000 #define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000 #define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR)// 0x000fc00c #define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
/* Display SSS register bits are different in A0 vs. B0 */ /* Display SSS register bits are different in A0 vs. B0 */
#define PSB_PWRGT_GFX_MASK 0x3 #define PSB_PWRGT_GFX_MASK 0x3
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0 #define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
@ -583,6 +577,6 @@
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000 #define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000 #define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000 #define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c #define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c #define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
#endif #endif