drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers
The POSTING_READ() calls were originally added to make sure the writes were flushed before any timing delays and across loops. Now that the code has settled a bit, let's remove them. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -217,7 +217,6 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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POSTING_READ(GMBUS2 + reg_offset);
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do {
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do {
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int ret;
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int ret;
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u32 val, loop = 0;
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u32 val, loop = 0;
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@ -261,7 +260,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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(msg->len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->len << GMBUS_BYTE_COUNT_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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POSTING_READ(GMBUS2 + reg_offset);
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while (len) {
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while (len) {
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int ret;
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int ret;
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u32 gmbus2;
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u32 gmbus2;
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@ -272,7 +270,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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} while (--len && ++loop < 4);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3 + reg_offset, val);
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I915_WRITE(GMBUS3 + reg_offset, val);
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POSTING_READ(GMBUS2 + reg_offset);
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ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
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ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
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(GMBUS_SATOER | GMBUS_HW_RDY),
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(GMBUS_SATOER | GMBUS_HW_RDY),
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