Merge 3.12-rc2 into staging-next.
This resolves the merge problem with two iio drivers that Stephen Rothwell pointed out. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
commit
e2aad1d571
|
@ -18,17 +18,17 @@ this byte for application use, with the following caveats:
|
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parameters containing user virtual addresses *must* have
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their top byte cleared before trapping to the kernel.
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(2) Tags are not guaranteed to be preserved when delivering
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signals. This means that signal handlers in applications
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making use of tags cannot rely on the tag information for
|
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user virtual addresses being maintained for fields inside
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siginfo_t. One exception to this rule is for signals raised
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in response to debug exceptions, where the tag information
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(2) Non-zero tags are not preserved when delivering signals.
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This means that signal handlers in applications making use
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of tags cannot rely on the tag information for user virtual
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addresses being maintained for fields inside siginfo_t.
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One exception to this rule is for signals raised in response
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to watchpoint debug exceptions, where the tag information
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will be preserved.
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(3) Special care should be taken when using tagged pointers,
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since it is likely that C compilers will not hazard two
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addresses differing only in the upper bits.
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virtual addresses differing only in the upper byte.
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The architecture prevents the use of a tagged PC, so the upper byte will
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be set to a sign-extension of bit 55 on exception return.
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@ -359,11 +359,9 @@ struct inode_operations {
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ssize_t (*listxattr) (struct dentry *, char *, size_t);
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int (*removexattr) (struct dentry *, const char *);
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void (*update_time)(struct inode *, struct timespec *, int);
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int (*atomic_open)(struct inode *, struct dentry *,
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int (*atomic_open)(struct inode *, struct dentry *, struct file *,
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unsigned open_flag, umode_t create_mode, int *opened);
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int (*tmpfile) (struct inode *, struct dentry *, umode_t);
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} ____cacheline_aligned;
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struct file *, unsigned open_flag,
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umode_t create_mode, int *opened);
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};
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Again, all methods are called without any locks being held, unless
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@ -470,9 +468,11 @@ otherwise noted.
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method the filesystem can look up, possibly create and open the file in
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one atomic operation. If it cannot perform this (e.g. the file type
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turned out to be wrong) it may signal this by returning 1 instead of
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usual 0 or -ve . This method is only called if the last
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component is negative or needs lookup. Cached positive dentries are
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still handled by f_op->open().
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usual 0 or -ve . This method is only called if the last component is
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negative or needs lookup. Cached positive dentries are still handled by
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f_op->open(). If the file was created, the FILE_CREATED flag should be
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set in "opened". In case of O_EXCL the method must only succeed if the
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file didn't exist and hence FILE_CREATED shall always be set on success.
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tmpfile: called in the end of O_TMPFILE open(). Optional, equivalent to
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atomically creating, opening and unlinking a file in given directory.
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|
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@ -1362,6 +1362,12 @@ To add ARP targets:
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To remove an ARP target:
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# echo -192.168.0.100 > /sys/class/net/bond0/bonding/arp_ip_target
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To configure the interval between learning packet transmits:
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# echo 12 > /sys/class/net/bond0/bonding/lp_interval
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NOTE: the lp_inteval is the number of seconds between instances where
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the bonding driver sends learning packets to each slaves peer switch. The
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default interval is 1 second.
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Example Configuration
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---------------------
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We begin with the same example that is shown in section 3.3,
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|
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@ -66,9 +66,7 @@ rq->cfs.load value, which is the sum of the weights of the tasks queued on the
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runqueue.
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CFS maintains a time-ordered rbtree, where all runnable tasks are sorted by the
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p->se.vruntime key (there is a subtraction using rq->cfs.min_vruntime to
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account for possible wraparounds). CFS picks the "leftmost" task from this
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tree and sticks to it.
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p->se.vruntime key. CFS picks the "leftmost" task from this tree and sticks to it.
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As the system progresses forwards, the executed tasks are put into the tree
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more and more to the right --- slowly but surely giving a chance for every task
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to become the "leftmost task" and thus get on the CPU within a deterministic
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|
|
2
Makefile
2
Makefile
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@ -1,7 +1,7 @@
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VERSION = 3
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PATCHLEVEL = 12
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SUBLEVEL = 0
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EXTRAVERSION = -rc1
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EXTRAVERSION = -rc2
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NAME = One Giant Leap for Frogkind
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# *DOCUMENTATION*
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|
|
|
@ -183,6 +183,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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am335x-evm.dtb \
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am335x-evmsk.dtb \
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am335x-bone.dtb \
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am335x-boneblack.dtb \
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am3517-evm.dtb \
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am3517_mt_ventoux.dtb \
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am43x-epos-evm.dtb
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|
|
|
@ -0,0 +1,262 @@
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "TI AM335x BeagleBone";
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||||
compatible = "ti,am335x-bone", "ti,am33xx";
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|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&dcdc2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkout2_pin>;
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
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||||
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
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0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
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||||
>;
|
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};
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||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
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||||
};
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||||
|
||||
uart0_pins: pinmux_uart0_pins {
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||||
pinctrl-single,pins = <
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||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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||||
>;
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||||
};
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||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
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||||
pinctrl-single,pins = <
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||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
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||||
>;
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||||
};
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||||
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cpsw_default: cpsw_default {
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||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
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||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
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||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
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||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
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0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
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||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
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||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
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||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
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||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
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||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
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0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
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0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
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0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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||||
/* Slave 1 reset value */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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||||
>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
|
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pinctrl-single,pins = <
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/* MDIO reset value */
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart0: serial@44e09000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
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||||
|
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status = "okay";
|
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};
|
||||
|
||||
musb: usb@47400000 {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401b00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401800 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@2 {
|
||||
label = "beaglebone:green:heartbeat";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beaglebone:green:mmc0";
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "beaglebone:green:usr2";
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "beaglebone:green:usr3";
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
|
@ -8,258 +8,4 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x BeagleBone";
|
||||
compatible = "ti,am335x-bone", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&dcdc2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkout2_pin>;
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
|
||||
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
|
||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart0: serial@44e09000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
musb: usb@47400000 {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401b00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401800 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@2 {
|
||||
label = "beaglebone:green:heartbeat";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beaglebone:green:mmc0";
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "beaglebone:green:usr2";
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "beaglebone:green:usr3";
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
#include "am335x-bone-common.dtsi"
|
||||
|
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include "am335x-bone-common.dtsi"
|
||||
|
||||
&ldo3_reg {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
|
@ -187,7 +187,7 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000e000 0x1000>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks 53>, <&clks 53>;
|
||||
clocks = <&clks 53>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -198,7 +198,7 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x1000f000 0x1000>;
|
||||
interrupts = <15>;
|
||||
clocks = <&clks 52>, <&clks 52>;
|
||||
clocks = <&clks 52>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -309,7 +309,7 @@
|
|||
compatible = "fsl,imx27-cspi";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 51>, <&clks 51>;
|
||||
clocks = <&clks 51>, <&clks 60>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -474,7 +474,7 @@
|
|||
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
|
||||
reg = <0x83fe0000 0x4000>;
|
||||
interrupts = <70>;
|
||||
clocks = <&clks 161>;
|
||||
clocks = <&clks 172>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -207,8 +207,8 @@
|
|||
#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
|
||||
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
|
||||
#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
|
||||
#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
|
||||
#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/ {
|
||||
model = "TI OMAP3 BeagleBoard xM";
|
||||
compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
|
||||
compatible = "ti,omap3-beagle-xm", "ti,omap3-beagle", "ti,omap3";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
|
|
|
@ -48,6 +48,15 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mcbsp2_pins: pinmux_mcbsp2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
|
||||
0x10e (PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
|
||||
0x110 (PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
|
||||
0x112 (PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
|
||||
|
@ -93,6 +102,11 @@
|
|||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&mcbsp2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp2_pins>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
|
|
|
@ -107,6 +107,19 @@
|
|||
*/
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
/* regulator for wl12xx on sdio5 */
|
||||
wl12xx_vmmc: wl12xx_vmmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_gpio>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwl1271";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio2 11 0>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_wkup {
|
||||
|
@ -235,6 +248,33 @@
|
|||
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
|
||||
* REVISIT: Are the pull-ups needed for GPIO 48 and 49?
|
||||
*/
|
||||
wl12xx_gpio: pinmux_wl12xx_gpio {
|
||||
pinctrl-single,pins = <
|
||||
0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
|
||||
0x2c (PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
|
||||
0x30 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
|
||||
0x32 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* wl12xx GPIO inputs and SDIO pins */
|
||||
wl12xx_pins: pinmux_wl12xx_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
|
||||
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
|
||||
0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
|
||||
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
|
||||
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
|
||||
0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
@ -314,8 +354,12 @@
|
|||
};
|
||||
|
||||
&mmc5 {
|
||||
ti,non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_pins>;
|
||||
vmmc-supply = <&wl12xx_vmmc>;
|
||||
non-removable;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
|
|
|
@ -140,6 +140,19 @@
|
|||
"DMic", "Digital Mic",
|
||||
"Digital Mic", "Digital Mic1 Bias";
|
||||
};
|
||||
|
||||
/* regulator for wl12xx on sdio5 */
|
||||
wl12xx_vmmc: wl12xx_vmmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_gpio>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwl1271";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio2 22 0>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_wkup {
|
||||
|
@ -295,6 +308,26 @@
|
|||
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
/* wl12xx GPIO output for WLAN_EN */
|
||||
wl12xx_gpio: pinmux_wl12xx_gpio {
|
||||
pinctrl-single,pins = <
|
||||
0x3c (PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* wl12xx GPIO inputs and SDIO pins */
|
||||
wl12xx_pins: pinmux_wl12xx_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
|
||||
0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
|
||||
0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
|
||||
0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
|
||||
0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
@ -420,8 +453,12 @@
|
|||
};
|
||||
|
||||
&mmc5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_pins>;
|
||||
vmmc-supply = <&wl12xx_vmmc>;
|
||||
non-removable;
|
||||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
cap-power-off-card;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
|
|
|
@ -637,7 +637,7 @@
|
|||
omap_dwc3@4a020000 {
|
||||
compatible = "ti,dwc3";
|
||||
ti,hwmods = "usb_otg_ss";
|
||||
reg = <0x4a020000 0x1000>;
|
||||
reg = <0x4a020000 0x10000>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
@ -645,17 +645,18 @@
|
|||
ranges;
|
||||
dwc3@4a030000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x4a030000 0x1000>;
|
||||
reg = <0x4a030000 0x10000>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy>, <&usb3_phy>;
|
||||
tx-fifo-resize;
|
||||
};
|
||||
};
|
||||
|
||||
ocp2scp {
|
||||
ocp2scp@4a080000 {
|
||||
compatible = "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x4a080000 0x20>;
|
||||
ranges;
|
||||
ti,hwmods = "ocp2scp1";
|
||||
usb2_phy: usb2phy@4a084000 {
|
||||
|
|
|
@ -36,6 +36,7 @@ CONFIG_ARCH_TEGRA_114_SOC=y
|
|||
CONFIG_TEGRA_PCI=y
|
||||
CONFIG_TEGRA_EMC_SCALING_ENABLE=y
|
||||
CONFIG_ARCH_U8500=y
|
||||
CONFIG_MACH_HREFV60=y
|
||||
CONFIG_MACH_SNOWBALL=y
|
||||
CONFIG_MACH_UX500_DT=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
|
@ -46,6 +47,7 @@ CONFIG_ARCH_ZYNQ=y
|
|||
CONFIG_SMP=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
|
|
|
@ -90,6 +90,7 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
|
|||
init.ops = &clk_fixup_mux_ops;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = 0;
|
||||
|
||||
fixup_mux->mux.reg = reg;
|
||||
fixup_mux->mux.shift = shift;
|
||||
|
|
|
@ -285,7 +285,7 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
|
||||
clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
|
||||
clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
|
||||
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
|
|
@ -328,7 +328,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
|
||||
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
|
||||
clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[iim_gate], "iim", NULL);
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
|
||||
|
@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
|
||||
clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
|
||||
spdif_sel, ARRAY_SIZE(spdif_sel));
|
||||
clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
|
||||
clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
|
||||
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
|
||||
|
|
|
@ -233,10 +233,15 @@ put_node:
|
|||
of_node_put(np);
|
||||
}
|
||||
|
||||
static void __init imx6q_opp_init(struct device *cpu_dev)
|
||||
static void __init imx6q_opp_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device *cpu_dev = get_cpu_device(0);
|
||||
|
||||
if (!cpu_dev) {
|
||||
pr_warn("failed to get cpu0 device\n");
|
||||
return;
|
||||
}
|
||||
np = of_node_get(cpu_dev->of_node);
|
||||
if (!np) {
|
||||
pr_warn("failed to find cpu0 node\n");
|
||||
|
@ -268,7 +273,7 @@ static void __init imx6q_init_late(void)
|
|||
imx6q_cpuidle_init();
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
|
||||
imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
|
||||
imx6q_opp_init();
|
||||
platform_device_register(&imx6q_cpufreq_pdev);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -117,6 +117,17 @@ void __init imx_init_l2cache(void)
|
|||
/* Configure the L2 PREFETCH and POWER registers */
|
||||
val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
|
||||
val |= 0x70800000;
|
||||
/*
|
||||
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
|
||||
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
|
||||
* But according to ARM PL310 errata: 752271
|
||||
* ID: 752271: Double linefill feature can cause data corruption
|
||||
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
|
||||
* Workaround: The only workaround to this erratum is to disable the
|
||||
* double linefill feature. This is the default behavior.
|
||||
*/
|
||||
if (cpu_is_imx6q())
|
||||
val &= ~(1 << 30 | 1 << 23);
|
||||
writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
|
||||
val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
|
||||
writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
|
||||
|
|
|
@ -1632,7 +1632,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
|
||||
CLK(NULL, "auxclk5_ck", &auxclk5_ck),
|
||||
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
|
||||
CLK("omap-gpmc", "fck", &dummy_ck),
|
||||
CLK("50000000.gpmc", "fck", &dummy_ck),
|
||||
CLK("omap_i2c.1", "ick", &dummy_ck),
|
||||
CLK("omap_i2c.2", "ick", &dummy_ck),
|
||||
CLK("omap_i2c.3", "ick", &dummy_ck),
|
||||
|
|
|
@ -143,7 +143,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
|
|||
* Call idle CPU cluster PM exit notifier chain
|
||||
* to restore GIC and wakeupgen context.
|
||||
*/
|
||||
if ((cx->mpu_state == PWRDM_POWER_RET) &&
|
||||
if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
|
||||
(cx->mpu_logic_state == PWRDM_POWER_OFF))
|
||||
cpu_cluster_pm_exit();
|
||||
|
||||
|
|
|
@ -1491,8 +1491,8 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
|
|||
*/
|
||||
ret = gpmc_cs_remap(cs, res.start);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
|
||||
cs, res.start);
|
||||
dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
|
||||
cs, &res.start);
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
|
@ -620,7 +620,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
|
|||
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
|
||||
"gpio_149", NULL, NULL, "safe_mode"),
|
||||
_OMAP3_MUXENTRY(UART1_RX, 151,
|
||||
"uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
|
||||
"uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
|
||||
"gpio_151", NULL, NULL, "safe_mode"),
|
||||
_OMAP3_MUXENTRY(UART1_TX, 148,
|
||||
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* OMAP4 SMP source file. It contains platform specific fucntions
|
||||
* OMAP4 SMP source file. It contains platform specific functions
|
||||
* needed for the linux smp kernel.
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
|
|
|
@ -158,7 +158,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
od = omap_device_alloc(pdev, hwmods, oh_cnt);
|
||||
if (!od) {
|
||||
if (IS_ERR(od)) {
|
||||
dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
|
||||
oh_name);
|
||||
ret = PTR_ERR(od);
|
||||
|
|
|
@ -289,7 +289,7 @@ static void collie_flash_exit(void)
|
|||
}
|
||||
|
||||
static struct flash_platform_data collie_flash_data = {
|
||||
.map_name = "cfi_probe",
|
||||
.map_name = "jedec_probe",
|
||||
.init = collie_flash_init,
|
||||
.set_vpp = collie_set_vpp,
|
||||
.exit = collie_flash_exit,
|
||||
|
|
|
@ -555,7 +555,7 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("pll2h", &pll2h_clk),
|
||||
|
||||
/* CPU clock */
|
||||
CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk),
|
||||
CLKDEV_DEV_ID("cpu0", &z_clk),
|
||||
|
||||
/* DIV6 */
|
||||
CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
|
||||
|
|
|
@ -616,7 +616,7 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
|
||||
CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
|
||||
|
|
|
@ -1,7 +1,3 @@
|
|||
menu "ST-Ericsson AB U300/U335 Platform"
|
||||
|
||||
comment "ST-Ericsson Mobile Platform Products"
|
||||
|
||||
config ARCH_U300
|
||||
bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
|
||||
depends on MMU
|
||||
|
@ -25,7 +21,9 @@ config ARCH_U300
|
|||
help
|
||||
Support for ST-Ericsson U300 series mobile platforms.
|
||||
|
||||
comment "ST-Ericsson U300/U335 Feature Selections"
|
||||
if ARCH_U300
|
||||
|
||||
menu "ST-Ericsson AB U300/U335 Platform"
|
||||
|
||||
config MACH_U300
|
||||
depends on ARCH_U300
|
||||
|
@ -53,3 +51,5 @@ config MACH_U300_SPIDUMMY
|
|||
SPI framework and ARM PL022 support.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
|
@ -69,6 +69,7 @@ static int __init ux500_l2x0_init(void)
|
|||
* some SMI service available.
|
||||
*/
|
||||
outer_cache.disable = NULL;
|
||||
outer_cache.set_debug = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -43,6 +43,6 @@
|
|||
COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
|
||||
COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
|
||||
|
||||
extern unsigned int elf_hwcap;
|
||||
extern unsigned long elf_hwcap;
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
@ -143,15 +143,26 @@ void machine_restart(char *cmd)
|
|||
|
||||
void __show_regs(struct pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
int i, top_reg;
|
||||
u64 lr, sp;
|
||||
|
||||
if (compat_user_mode(regs)) {
|
||||
lr = regs->compat_lr;
|
||||
sp = regs->compat_sp;
|
||||
top_reg = 12;
|
||||
} else {
|
||||
lr = regs->regs[30];
|
||||
sp = regs->sp;
|
||||
top_reg = 29;
|
||||
}
|
||||
|
||||
show_regs_print_info(KERN_DEFAULT);
|
||||
print_symbol("PC is at %s\n", instruction_pointer(regs));
|
||||
print_symbol("LR is at %s\n", regs->regs[30]);
|
||||
print_symbol("LR is at %s\n", lr);
|
||||
printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
|
||||
regs->pc, regs->regs[30], regs->pstate);
|
||||
printk("sp : %016llx\n", regs->sp);
|
||||
for (i = 29; i >= 0; i--) {
|
||||
regs->pc, lr, regs->pstate);
|
||||
printk("sp : %016llx\n", sp);
|
||||
for (i = top_reg; i >= 0; i--) {
|
||||
printk("x%-2d: %016llx ", i, regs->regs[i]);
|
||||
if (i % 2 == 0)
|
||||
printk("\n");
|
||||
|
|
|
@ -57,7 +57,7 @@
|
|||
unsigned int processor_id;
|
||||
EXPORT_SYMBOL(processor_id);
|
||||
|
||||
unsigned int elf_hwcap __read_mostly;
|
||||
unsigned long elf_hwcap __read_mostly;
|
||||
EXPORT_SYMBOL_GPL(elf_hwcap);
|
||||
|
||||
static const char *cpu_name;
|
||||
|
|
|
@ -130,7 +130,7 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
|
|||
force_sig_info(sig, &si, tsk);
|
||||
}
|
||||
|
||||
void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
|
||||
static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
struct mm_struct *mm = tsk->active_mm;
|
||||
|
|
|
@ -288,9 +288,6 @@ endif
|
|||
vmlinux.32: vmlinux
|
||||
$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
|
||||
|
||||
|
||||
#obj-$(CONFIG_KPROBES) += kprobes.o
|
||||
|
||||
#
|
||||
# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
|
||||
# ELF files from 32-bit files by conversion.
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
|
||||
/* control register offsets */
|
||||
|
@ -358,7 +359,7 @@ static inline int au1200_coherency_bug(void)
|
|||
{
|
||||
#if defined(CONFIG_DMA_COHERENT)
|
||||
/* Au1200 AB USB does not support coherent memory */
|
||||
if (!(read_c0_prid() & 0xff)) {
|
||||
if (!(read_c0_prid() & PRID_REV_MASK)) {
|
||||
printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
|
||||
printk(KERN_INFO "Au1200 USB: update your board or re-configure"
|
||||
" the kernel\n");
|
||||
|
|
|
@ -306,14 +306,14 @@ void __init bcm63xx_cpu_init(void)
|
|||
|
||||
switch (c->cputype) {
|
||||
case CPU_BMIPS3300:
|
||||
if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
|
||||
if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
|
||||
__cpu_name[cpu] = "Broadcom BCM6338";
|
||||
/* fall-through */
|
||||
case CPU_BMIPS32:
|
||||
chipid_reg = BCM_6345_PERF_BASE;
|
||||
break;
|
||||
case CPU_BMIPS4350:
|
||||
switch ((read_c0_prid() & 0xff)) {
|
||||
switch ((read_c0_prid() & PRID_REV_MASK)) {
|
||||
case 0x04:
|
||||
chipid_reg = BCM_3368_PERF_BASE;
|
||||
break;
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <asm/dec/prom.h>
|
||||
|
|
|
@ -13,12 +13,6 @@
|
|||
#include <asm/cpu-info.h>
|
||||
#include <cpu-feature-overrides.h>
|
||||
|
||||
#ifndef current_cpu_type
|
||||
#define current_cpu_type() current_cpu_data.cputype
|
||||
#endif
|
||||
|
||||
#define boot_cpu_type() cpu_data[0].cputype
|
||||
|
||||
/*
|
||||
* SMP assumption: Options of CPU 0 are a superset of all processors.
|
||||
* This is true for all known MIPS systems.
|
||||
|
|
|
@ -84,6 +84,7 @@ struct cpuinfo_mips {
|
|||
extern struct cpuinfo_mips cpu_data[];
|
||||
#define current_cpu_data cpu_data[smp_processor_id()]
|
||||
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
|
||||
#define boot_cpu_data cpu_data[0]
|
||||
|
||||
extern void cpu_probe(void);
|
||||
extern void cpu_report(void);
|
||||
|
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef __ASM_CPU_TYPE_H
|
||||
#define __ASM_CPU_TYPE_H
|
||||
|
||||
#include <linux/smp.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
static inline int __pure __get_cpu_type(const int cpu_type)
|
||||
{
|
||||
switch (cpu_type) {
|
||||
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
|
||||
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
|
||||
case CPU_LOONGSON2:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
|
||||
case CPU_LOONGSON1:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
|
||||
case CPU_4KC:
|
||||
case CPU_ALCHEMY:
|
||||
case CPU_BMIPS3300:
|
||||
case CPU_BMIPS4350:
|
||||
case CPU_PR4450:
|
||||
case CPU_BMIPS32:
|
||||
case CPU_JZRISC:
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
|
||||
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
|
||||
case CPU_4KEC:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
|
||||
case CPU_4KSC:
|
||||
case CPU_24K:
|
||||
case CPU_34K:
|
||||
case CPU_1004K:
|
||||
case CPU_74K:
|
||||
case CPU_M14KC:
|
||||
case CPU_M14KEC:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
|
||||
case CPU_5KC:
|
||||
case CPU_5KE:
|
||||
case CPU_20KC:
|
||||
case CPU_25KF:
|
||||
case CPU_SB1:
|
||||
case CPU_SB1A:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
|
||||
/*
|
||||
* All MIPS64 R2 processors have their own special symbols. That is,
|
||||
* there currently is no pure R2 core
|
||||
*/
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R3000
|
||||
case CPU_R2000:
|
||||
case CPU_R3000:
|
||||
case CPU_R3000A:
|
||||
case CPU_R3041:
|
||||
case CPU_R3051:
|
||||
case CPU_R3052:
|
||||
case CPU_R3081:
|
||||
case CPU_R3081E:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_TX39XX
|
||||
case CPU_TX3912:
|
||||
case CPU_TX3922:
|
||||
case CPU_TX3927:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_VR41XX
|
||||
case CPU_VR41XX:
|
||||
case CPU_VR4111:
|
||||
case CPU_VR4121:
|
||||
case CPU_VR4122:
|
||||
case CPU_VR4131:
|
||||
case CPU_VR4133:
|
||||
case CPU_VR4181:
|
||||
case CPU_VR4181A:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R4300
|
||||
case CPU_R4300:
|
||||
case CPU_R4310:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R4X00
|
||||
case CPU_R4000PC:
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
case CPU_R4200:
|
||||
case CPU_R4400PC:
|
||||
case CPU_R4400SC:
|
||||
case CPU_R4400MC:
|
||||
case CPU_R4600:
|
||||
case CPU_R4700:
|
||||
case CPU_R4640:
|
||||
case CPU_R4650:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_TX49XX
|
||||
case CPU_TX49XX:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R5000
|
||||
case CPU_R5000:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R5432
|
||||
case CPU_R5432:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R5500
|
||||
case CPU_R5500:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R6000
|
||||
case CPU_R6000:
|
||||
case CPU_R6000A:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_NEVADA
|
||||
case CPU_NEVADA:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R8000
|
||||
case CPU_R8000:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_R10000
|
||||
case CPU_R10000:
|
||||
case CPU_R12000:
|
||||
case CPU_R14000:
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HAS_CPU_RM7000
|
||||
case CPU_RM7000:
|
||||
case CPU_SR71000:
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HAS_CPU_RM9000
|
||||
case CPU_RM9000:
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HAS_CPU_SB1
|
||||
case CPU_SB1:
|
||||
case CPU_SB1A:
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
case CPU_CAVIUM_OCTEON:
|
||||
case CPU_CAVIUM_OCTEON_PLUS:
|
||||
case CPU_CAVIUM_OCTEON2:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
|
||||
case CPU_BMIPS4380:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
|
||||
case CPU_BMIPS5000:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_XLP
|
||||
case CPU_XLP:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_XLR
|
||||
case CPU_XLR:
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
unreachable();
|
||||
}
|
||||
|
||||
return cpu_type;
|
||||
}
|
||||
|
||||
static inline int __pure current_cpu_type(void)
|
||||
{
|
||||
const int cpu_type = current_cpu_data.cputype;
|
||||
|
||||
return __get_cpu_type(cpu_type);
|
||||
}
|
||||
|
||||
static inline int __pure boot_cpu_type(void)
|
||||
{
|
||||
const int cpu_type = cpu_data[0].cputype;
|
||||
|
||||
return __get_cpu_type(cpu_type);
|
||||
}
|
||||
|
||||
#endif /* __ASM_CPU_TYPE_H */
|
|
@ -3,15 +3,14 @@
|
|||
* various MIPS cpu types.
|
||||
*
|
||||
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
|
||||
* Copyright (C) 2004 Maciej W. Rozycki
|
||||
* Copyright (C) 2004, 2013 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef _ASM_CPU_H
|
||||
#define _ASM_CPU_H
|
||||
|
||||
/* Assigned Company values for bits 23:16 of the PRId Register
|
||||
(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
|
||||
MTI, the PRId register is defined in this (backwards compatible)
|
||||
way:
|
||||
/*
|
||||
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
|
||||
register 15, select 0) is defined in this (backwards compatible) way:
|
||||
|
||||
+----------------+----------------+----------------+----------------+
|
||||
| Company Options| Company ID | Processor ID | Revision |
|
||||
|
@ -23,6 +22,14 @@
|
|||
spec.
|
||||
*/
|
||||
|
||||
#define PRID_OPT_MASK 0xff000000
|
||||
|
||||
/*
|
||||
* Assigned Company values for bits 23:16 of the PRId register.
|
||||
*/
|
||||
|
||||
#define PRID_COMP_MASK 0xff0000
|
||||
|
||||
#define PRID_COMP_LEGACY 0x000000
|
||||
#define PRID_COMP_MIPS 0x010000
|
||||
#define PRID_COMP_BROADCOM 0x020000
|
||||
|
@ -38,10 +45,17 @@
|
|||
#define PRID_COMP_INGENIC 0xd00000
|
||||
|
||||
/*
|
||||
* Assigned values for the product ID register. In order to detect a
|
||||
* certain CPU type exactly eventually additional registers may need to
|
||||
* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
|
||||
* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
|
||||
* register. In order to detect a certain CPU type exactly eventually
|
||||
* additional registers may need to be examined.
|
||||
*/
|
||||
|
||||
#define PRID_IMP_MASK 0xff00
|
||||
|
||||
/*
|
||||
* These are valid when 23:16 == PRID_COMP_LEGACY
|
||||
*/
|
||||
|
||||
#define PRID_IMP_R2000 0x0100
|
||||
#define PRID_IMP_AU1_REV1 0x0100
|
||||
#define PRID_IMP_AU1_REV2 0x0200
|
||||
|
@ -182,11 +196,15 @@
|
|||
#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
|
||||
|
||||
/*
|
||||
* Definitions for 7:0 on legacy processors
|
||||
* Particular Revision values for bits 7:0 of the PRId register.
|
||||
*/
|
||||
|
||||
#define PRID_REV_MASK 0x00ff
|
||||
|
||||
/*
|
||||
* Definitions for 7:0 on legacy processors
|
||||
*/
|
||||
|
||||
#define PRID_REV_TX4927 0x0022
|
||||
#define PRID_REV_TX4937 0x0030
|
||||
#define PRID_REV_R4400 0x0040
|
||||
|
@ -227,6 +245,8 @@
|
|||
* 31 16 15 8 7 0
|
||||
*/
|
||||
|
||||
#define FPIR_IMP_MASK 0xff00
|
||||
|
||||
#define FPIR_IMP_NONE 0x0000
|
||||
|
||||
enum cpu_type_enum {
|
||||
|
|
|
@ -43,6 +43,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
|
||||
/* cpu pipeline flush */
|
||||
void static inline au_sync(void)
|
||||
{
|
||||
|
@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
|
|||
|
||||
static inline int alchemy_get_cputype(void)
|
||||
{
|
||||
switch (read_c0_prid() & 0xffff0000) {
|
||||
switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
|
||||
case 0x00030000:
|
||||
return ALCHEMY_CPU_AU1000;
|
||||
break;
|
||||
|
|
|
@ -8,6 +8,8 @@
|
|||
#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#include <asm/cpu.h>
|
||||
|
||||
/*
|
||||
* IP22 with a variety of processors so we can't use defaults for everything.
|
||||
*/
|
||||
|
|
|
@ -8,6 +8,8 @@
|
|||
#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#include <asm/cpu.h>
|
||||
|
||||
/*
|
||||
* IP27 only comes with R10000 family processors all using the same config
|
||||
*/
|
||||
|
|
|
@ -9,6 +9,8 @@
|
|||
#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#include <asm/cpu.h>
|
||||
|
||||
/*
|
||||
* IP28 only comes with R10000 family processors all using the same config
|
||||
*/
|
||||
|
|
|
@ -603,6 +603,13 @@
|
|||
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
|
||||
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
|
||||
|
||||
#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
|
||||
#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
|
||||
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
|
||||
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
|
||||
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
|
||||
#define MIPS_CONF5_K (_ULCAST_(1) << 30)
|
||||
|
||||
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
|
||||
|
||||
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
|
||||
|
|
|
@ -83,6 +83,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
|
|||
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
enum pci_mmap_state mmap_state, int write_combine);
|
||||
|
||||
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
|
||||
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc, resource_size_t *start,
|
||||
resource_size_t *end)
|
||||
{
|
||||
phys_t size = resource_size(rsrc);
|
||||
|
||||
*start = fixup_bigphys_addr(rsrc->start, size);
|
||||
*end = rsrc->start + size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dynamic DMA mapping stuff.
|
||||
* MIPS has everything mapped statically.
|
||||
|
|
|
@ -10,7 +10,9 @@
|
|||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/cpu-type.h>
|
||||
|
||||
/*
|
||||
* This is the clock rate of the i8253 PIT. A MIPS system may not have
|
||||
|
@ -33,9 +35,38 @@
|
|||
|
||||
typedef unsigned int cycles_t;
|
||||
|
||||
/*
|
||||
* On R4000/R4400 before version 5.0 an erratum exists such that if the
|
||||
* cycle counter is read in the exact moment that it is matching the
|
||||
* compare register, no interrupt will be generated.
|
||||
*
|
||||
* There is a suggested workaround and also the erratum can't strike if
|
||||
* the compare interrupt isn't being used as the clock source device.
|
||||
* However for now the implementaton of this function doesn't get these
|
||||
* fine details right.
|
||||
*/
|
||||
static inline cycles_t get_cycles(void)
|
||||
{
|
||||
return 0;
|
||||
switch (boot_cpu_type()) {
|
||||
case CPU_R4400PC:
|
||||
case CPU_R4400SC:
|
||||
case CPU_R4400MC:
|
||||
if ((read_c0_prid() & 0xff) >= 0x0050)
|
||||
return read_c0_count();
|
||||
break;
|
||||
|
||||
case CPU_R4000PC:
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
break;
|
||||
|
||||
default:
|
||||
if (cpu_has_counter)
|
||||
return read_c0_count();
|
||||
break;
|
||||
}
|
||||
|
||||
return 0; /* no usable counter */
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#ifndef _ASM_VGA_H
|
||||
#define _ASM_VGA_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
/*
|
||||
|
@ -13,7 +14,7 @@
|
|||
* access the videoram directly without any black magic.
|
||||
*/
|
||||
|
||||
#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x))
|
||||
#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
|
||||
|
||||
#define vga_readb(x) (*(x))
|
||||
#define vga_writeb(x, y) (*(y) = (x))
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include <asm/bugs.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/watch.h>
|
||||
|
@ -55,7 +56,7 @@ static inline void check_errata(void)
|
|||
{
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_34K:
|
||||
/*
|
||||
* Erratum "RPS May Cause Incorrect Instruction Execution"
|
||||
|
@ -122,7 +123,7 @@ static inline unsigned long cpu_get_fpu_id(void)
|
|||
*/
|
||||
static inline int __cpu_has_fpu(void)
|
||||
{
|
||||
return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
|
||||
return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
|
||||
}
|
||||
|
||||
static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
|
||||
|
@ -290,6 +291,17 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
|
|||
return config4 & MIPS_CONF_M;
|
||||
}
|
||||
|
||||
static inline unsigned int decode_config5(struct cpuinfo_mips *c)
|
||||
{
|
||||
unsigned int config5;
|
||||
|
||||
config5 = read_c0_config5();
|
||||
config5 &= ~MIPS_CONF5_UFR;
|
||||
write_c0_config5(config5);
|
||||
|
||||
return config5 & MIPS_CONF_M;
|
||||
}
|
||||
|
||||
static void decode_configs(struct cpuinfo_mips *c)
|
||||
{
|
||||
int ok;
|
||||
|
@ -310,6 +322,8 @@ static void decode_configs(struct cpuinfo_mips *c)
|
|||
ok = decode_config3(c);
|
||||
if (ok)
|
||||
ok = decode_config4(c);
|
||||
if (ok)
|
||||
ok = decode_config5(c);
|
||||
|
||||
mips_probe_watch_registers(c);
|
||||
|
||||
|
@ -322,7 +336,7 @@ static void decode_configs(struct cpuinfo_mips *c)
|
|||
|
||||
static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_R2000:
|
||||
c->cputype = CPU_R2000;
|
||||
__cpu_name[cpu] = "R2000";
|
||||
|
@ -333,7 +347,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->tlbsize = 64;
|
||||
break;
|
||||
case PRID_IMP_R3000:
|
||||
if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
|
||||
if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
|
||||
if (cpu_has_confreg()) {
|
||||
c->cputype = CPU_R3081E;
|
||||
__cpu_name[cpu] = "R3081";
|
||||
|
@ -353,7 +367,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
break;
|
||||
case PRID_IMP_R4000:
|
||||
if (read_c0_config() & CONF_SC) {
|
||||
if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
|
||||
if ((c->processor_id & PRID_REV_MASK) >=
|
||||
PRID_REV_R4400) {
|
||||
c->cputype = CPU_R4400PC;
|
||||
__cpu_name[cpu] = "R4400PC";
|
||||
} else {
|
||||
|
@ -361,7 +376,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "R4000PC";
|
||||
}
|
||||
} else {
|
||||
if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
|
||||
if ((c->processor_id & PRID_REV_MASK) >=
|
||||
PRID_REV_R4400) {
|
||||
c->cputype = CPU_R4400SC;
|
||||
__cpu_name[cpu] = "R4400SC";
|
||||
} else {
|
||||
|
@ -454,7 +470,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "TX3927";
|
||||
c->tlbsize = 64;
|
||||
} else {
|
||||
switch (c->processor_id & 0xff) {
|
||||
switch (c->processor_id & PRID_REV_MASK) {
|
||||
case PRID_REV_TX3912:
|
||||
c->cputype = CPU_TX3912;
|
||||
__cpu_name[cpu] = "TX3912";
|
||||
|
@ -640,7 +656,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_4KC:
|
||||
c->cputype = CPU_4KC;
|
||||
__cpu_name[cpu] = "MIPS 4Kc";
|
||||
|
@ -711,7 +727,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_AU1_REV1:
|
||||
case PRID_IMP_AU1_REV2:
|
||||
c->cputype = CPU_ALCHEMY;
|
||||
|
@ -730,7 +746,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
break;
|
||||
case 4:
|
||||
__cpu_name[cpu] = "Au1200";
|
||||
if ((c->processor_id & 0xff) == 2)
|
||||
if ((c->processor_id & PRID_REV_MASK) == 2)
|
||||
__cpu_name[cpu] = "Au1250";
|
||||
break;
|
||||
case 5:
|
||||
|
@ -748,12 +764,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
{
|
||||
decode_configs(c);
|
||||
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_SB1:
|
||||
c->cputype = CPU_SB1;
|
||||
__cpu_name[cpu] = "SiByte SB1";
|
||||
/* FPU in pass1 is known to have issues. */
|
||||
if ((c->processor_id & 0xff) < 0x02)
|
||||
if ((c->processor_id & PRID_REV_MASK) < 0x02)
|
||||
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
|
||||
break;
|
||||
case PRID_IMP_SB1A:
|
||||
|
@ -766,7 +782,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_SR71000:
|
||||
c->cputype = CPU_SR71000;
|
||||
__cpu_name[cpu] = "Sandcraft SR71000";
|
||||
|
@ -779,7 +795,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_PR4450:
|
||||
c->cputype = CPU_PR4450;
|
||||
__cpu_name[cpu] = "Philips PR4450";
|
||||
|
@ -791,7 +807,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_BMIPS32_REV4:
|
||||
case PRID_IMP_BMIPS32_REV8:
|
||||
c->cputype = CPU_BMIPS32;
|
||||
|
@ -806,7 +822,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
set_elf_platform(cpu, "bmips3300");
|
||||
break;
|
||||
case PRID_IMP_BMIPS43XX: {
|
||||
int rev = c->processor_id & 0xff;
|
||||
int rev = c->processor_id & PRID_REV_MASK;
|
||||
|
||||
if (rev >= PRID_REV_BMIPS4380_LO &&
|
||||
rev <= PRID_REV_BMIPS4380_HI) {
|
||||
|
@ -832,7 +848,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
|
||||
{
|
||||
decode_configs(c);
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_CAVIUM_CN38XX:
|
||||
case PRID_IMP_CAVIUM_CN31XX:
|
||||
case PRID_IMP_CAVIUM_CN30XX:
|
||||
|
@ -875,7 +891,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
decode_configs(c);
|
||||
/* JZRISC does not implement the CP0 counter. */
|
||||
c->options &= ~MIPS_CPU_COUNTER;
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_JZRISC:
|
||||
c->cputype = CPU_JZRISC;
|
||||
__cpu_name[cpu] = "Ingenic JZRISC";
|
||||
|
@ -890,7 +906,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
|
|||
{
|
||||
decode_configs(c);
|
||||
|
||||
if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
|
||||
if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
|
||||
c->cputype = CPU_ALCHEMY;
|
||||
__cpu_name[cpu] = "Au1300";
|
||||
/* following stuff is not for Alchemy */
|
||||
|
@ -905,7 +921,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
|
|||
MIPS_CPU_EJTAG |
|
||||
MIPS_CPU_LLSC);
|
||||
|
||||
switch (c->processor_id & 0xff00) {
|
||||
switch (c->processor_id & PRID_IMP_MASK) {
|
||||
case PRID_IMP_NETLOGIC_XLP2XX:
|
||||
c->cputype = CPU_XLP;
|
||||
__cpu_name[cpu] = "Broadcom XLPII";
|
||||
|
@ -984,7 +1000,7 @@ void cpu_probe(void)
|
|||
c->cputype = CPU_UNKNOWN;
|
||||
|
||||
c->processor_id = read_c0_prid();
|
||||
switch (c->processor_id & 0xff0000) {
|
||||
switch (c->processor_id & PRID_COMP_MASK) {
|
||||
case PRID_COMP_LEGACY:
|
||||
cpu_probe_legacy(c, cpu);
|
||||
break;
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
|
@ -136,7 +137,7 @@ void __init check_wait(void)
|
|||
return;
|
||||
}
|
||||
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_R3081:
|
||||
case CPU_R3081E:
|
||||
cpu_wait = r3081_wait;
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/export.h>
|
||||
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/smtc_ipi.h>
|
||||
#include <asm/time.h>
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <asm/break.h>
|
||||
#include <asm/cop2.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/dsp.h>
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/fpu_emulator.h>
|
||||
|
@ -622,7 +623,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
|
|||
regs->regs[rt] = read_c0_count();
|
||||
return 0;
|
||||
case 3: /* Count register resolution */
|
||||
switch (current_cpu_data.cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_20KC:
|
||||
case CPU_25KF:
|
||||
regs->regs[rt] = 1;
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <asm/bootinfo.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/r4kcache.h>
|
||||
|
@ -186,9 +187,10 @@ static void probe_octeon(void)
|
|||
unsigned long dcache_size;
|
||||
unsigned int config1;
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
int cputype = current_cpu_type();
|
||||
|
||||
config1 = read_c0_config1();
|
||||
switch (c->cputype) {
|
||||
switch (cputype) {
|
||||
case CPU_CAVIUM_OCTEON:
|
||||
case CPU_CAVIUM_OCTEON_PLUS:
|
||||
c->icache.linesz = 2 << ((config1 >> 19) & 7);
|
||||
|
@ -199,7 +201,7 @@ static void probe_octeon(void)
|
|||
c->icache.sets * c->icache.ways * c->icache.linesz;
|
||||
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
|
||||
c->dcache.linesz = 128;
|
||||
if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
|
||||
if (cputype == CPU_CAVIUM_OCTEON_PLUS)
|
||||
c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
|
||||
else
|
||||
c->dcache.sets = 1; /* CN3XXX has one Dcache set */
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/highmem.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/preempt.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/mm.h>
|
||||
|
@ -24,6 +25,7 @@
|
|||
#include <asm/cacheops.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
@ -601,6 +603,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
|||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
preempt_disable();
|
||||
if (cpu_has_inclusive_pcaches) {
|
||||
if (size >= scache_size)
|
||||
r4k_blast_scache();
|
||||
|
@ -621,6 +624,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
|||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
blast_dcache_range(addr, addr + size);
|
||||
}
|
||||
preempt_enable();
|
||||
|
||||
bc_wback_inv(addr, size);
|
||||
__sync();
|
||||
|
@ -631,6 +635,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
|
|||
/* Catch bad driver code */
|
||||
BUG_ON(size == 0);
|
||||
|
||||
preempt_disable();
|
||||
if (cpu_has_inclusive_pcaches) {
|
||||
if (size >= scache_size)
|
||||
r4k_blast_scache();
|
||||
|
@ -655,6 +660,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
|
|||
R4600_HIT_CACHEOP_WAR_IMPL;
|
||||
blast_inv_dcache_range(addr, addr + size);
|
||||
}
|
||||
preempt_enable();
|
||||
|
||||
bc_inv(addr, size);
|
||||
__sync();
|
||||
|
@ -780,21 +786,31 @@ static inline void rm7k_erratum31(void)
|
|||
|
||||
static inline void alias_74k_erratum(struct cpuinfo_mips *c)
|
||||
{
|
||||
unsigned int imp = c->processor_id & PRID_IMP_MASK;
|
||||
unsigned int rev = c->processor_id & PRID_REV_MASK;
|
||||
|
||||
/*
|
||||
* Early versions of the 74K do not update the cache tags on a
|
||||
* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
|
||||
* aliases. In this case it is better to treat the cache as always
|
||||
* having aliases.
|
||||
*/
|
||||
if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
|
||||
switch (imp) {
|
||||
case PRID_IMP_74K:
|
||||
if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
|
||||
c->dcache.flags |= MIPS_CACHE_VTAG;
|
||||
if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
|
||||
if (rev == PRID_REV_ENCODE_332(2, 4, 0))
|
||||
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
|
||||
if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
|
||||
((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
|
||||
break;
|
||||
case PRID_IMP_1074K:
|
||||
if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
|
||||
c->dcache.flags |= MIPS_CACHE_VTAG;
|
||||
write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static char *way_string[] = { NULL, "direct mapped", "2-way",
|
||||
|
@ -809,7 +825,7 @@ static void probe_pcache(void)
|
|||
unsigned long config1;
|
||||
unsigned int lsize;
|
||||
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_R4600: /* QED style two way caches? */
|
||||
case CPU_R4700:
|
||||
case CPU_R5000:
|
||||
|
@ -1025,7 +1041,8 @@ static void probe_pcache(void)
|
|||
* presumably no vendor is shipping his hardware in the "bad"
|
||||
* configuration.
|
||||
*/
|
||||
if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
|
||||
if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
|
||||
(prid & PRID_REV_MASK) < PRID_REV_R4400 &&
|
||||
!(config & CONF_SC) && c->icache.linesz != 16 &&
|
||||
PAGE_SIZE <= 0x8000)
|
||||
panic("Improper R4000SC processor configuration detected");
|
||||
|
@ -1045,7 +1062,7 @@ static void probe_pcache(void)
|
|||
* normally they'd suffer from aliases but magic in the hardware deals
|
||||
* with that for us so we don't need to take care ourselves.
|
||||
*/
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_20KC:
|
||||
case CPU_25KF:
|
||||
case CPU_SB1:
|
||||
|
@ -1065,7 +1082,7 @@ static void probe_pcache(void)
|
|||
case CPU_34K:
|
||||
case CPU_74K:
|
||||
case CPU_1004K:
|
||||
if (c->cputype == CPU_74K)
|
||||
if (current_cpu_type() == CPU_74K)
|
||||
alias_74k_erratum(c);
|
||||
if ((read_c0_config7() & (1 << 16))) {
|
||||
/* effectively physically indexed dcache,
|
||||
|
@ -1078,7 +1095,7 @@ static void probe_pcache(void)
|
|||
c->dcache.flags |= MIPS_CACHE_ALIASES;
|
||||
}
|
||||
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_20KC:
|
||||
/*
|
||||
* Some older 20Kc chips doesn't have the 'VI' bit in
|
||||
|
@ -1207,7 +1224,7 @@ static void setup_scache(void)
|
|||
* processors don't have a S-cache that would be relevant to the
|
||||
* Linux memory management.
|
||||
*/
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_R4000SC:
|
||||
case CPU_R4000MC:
|
||||
case CPU_R4400SC:
|
||||
|
@ -1384,9 +1401,8 @@ static void r4k_cache_error_setup(void)
|
|||
{
|
||||
extern char __weak except_vec2_generic;
|
||||
extern char __weak except_vec2_sb1;
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_SB1:
|
||||
case CPU_SB1A:
|
||||
set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/highmem.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <dma-coherence.h>
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
|
||||
#include <asm/bugs.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/inst.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/page.h>
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/bcache.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
|
|||
unsigned int tmp;
|
||||
|
||||
/* Check the bypass bit (L2B) */
|
||||
switch (c->cputype) {
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_34K:
|
||||
case CPU_74K:
|
||||
case CPU_1004K:
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/module.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/cache.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/war.h>
|
||||
#include <asm/uasm.h>
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/timex.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
#include <asm/hardirq.h>
|
||||
|
@ -76,7 +77,7 @@ static void __init estimate_frequencies(void)
|
|||
#endif
|
||||
|
||||
#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
|
||||
|
||||
/*
|
||||
* XXXKYMA: hardwire the CPU frequency to Host Freq/4
|
||||
|
@ -169,7 +170,7 @@ unsigned int get_c0_compare_int(void)
|
|||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
|
||||
unsigned int freq;
|
||||
|
||||
estimate_frequencies();
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
*/
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/irq.h>
|
||||
|
@ -34,7 +35,7 @@ static void __iomem *status_reg = (void __iomem *)0xbf000410;
|
|||
*/
|
||||
static unsigned int __init estimate_cpu_frequency(void)
|
||||
{
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
|
||||
unsigned int tick = 0;
|
||||
unsigned int freq;
|
||||
unsigned int orig;
|
||||
|
|
|
@ -36,6 +36,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/netlogic/xlr/fmn.h>
|
||||
#include <asm/netlogic/xlr/xlr.h>
|
||||
|
@ -187,7 +188,7 @@ void xlr_board_info_setup(void)
|
|||
int processor_id, num_core;
|
||||
|
||||
num_core = hweight32(nlm_current_node()->coremask);
|
||||
processor_id = read_c0_prid() & 0xff00;
|
||||
processor_id = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
setup_cpu_fmninfo(cpu, num_core);
|
||||
switch (processor_id) {
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/oprofile.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/cpu-type.h>
|
||||
|
||||
#include "op_impl.h"
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/vt.h>
|
||||
|
||||
#include <asm/sibyte/bcm1480_regs.h>
|
||||
#include <asm/sibyte/bcm1480_scd.h>
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/string.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
|
@ -119,7 +120,7 @@ void __init bcm1480_setup(void)
|
|||
uint64_t sys_rev;
|
||||
int plldiv;
|
||||
|
||||
sb1_pass = read_c0_prid() & 0xff;
|
||||
sb1_pass = read_c0_prid() & PRID_REV_MASK;
|
||||
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
|
||||
soc_type = SYS_SOC_TYPE(sys_rev);
|
||||
part_type = G_SYS_PART(sys_rev);
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/string.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/sibyte/sb1250.h>
|
||||
|
@ -182,7 +183,7 @@ void __init sb1250_setup(void)
|
|||
int plldiv;
|
||||
int bad_config = 0;
|
||||
|
||||
sb1_pass = read_c0_prid() & 0xff;
|
||||
sb1_pass = read_c0_prid() & PRID_REV_MASK;
|
||||
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
|
||||
soc_type = SYS_SOC_TYPE(sys_rev);
|
||||
soc_pass = G_SYS_REVISION(sys_rev);
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#endif
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/sni.h>
|
||||
|
@ -173,7 +174,7 @@ void __init plat_mem_setup(void)
|
|||
system_type = "RM300-Cxx";
|
||||
break;
|
||||
case SNI_BRD_PCI_DESKTOP:
|
||||
switch (read_c0_prid() & 0xff00) {
|
||||
switch (read_c0_prid() & PRID_IMP_MASK) {
|
||||
case PRID_IMP_R4600:
|
||||
case PRID_IMP_R4700:
|
||||
system_type = "RM200-C20";
|
||||
|
|
|
@ -361,7 +361,7 @@ config CMDLINE_OVERRIDE
|
|||
|
||||
config VMALLOC_RESERVE
|
||||
hex
|
||||
default 0x1000000
|
||||
default 0x2000000
|
||||
|
||||
config HARDWALL
|
||||
bool "Hardwall support to allow access to user dynamic network"
|
||||
|
|
|
@ -460,8 +460,7 @@ struct adjust_timestamp_aux_param {
|
|||
int64_t nsec;
|
||||
};
|
||||
|
||||
int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t * context,
|
||||
int64_t nsec)
|
||||
int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t *context, int64_t nsec)
|
||||
{
|
||||
struct adjust_timestamp_aux_param temp;
|
||||
struct adjust_timestamp_aux_param *params = &temp;
|
||||
|
@ -475,25 +474,6 @@ int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t * context,
|
|||
|
||||
EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_aux);
|
||||
|
||||
struct adjust_timestamp_freq_param {
|
||||
int32_t ppb;
|
||||
};
|
||||
|
||||
int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t * context,
|
||||
int32_t ppb)
|
||||
{
|
||||
struct adjust_timestamp_freq_param temp;
|
||||
struct adjust_timestamp_freq_param *params = &temp;
|
||||
|
||||
params->ppb = ppb;
|
||||
|
||||
return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
|
||||
sizeof(*params),
|
||||
GXIO_MPIPE_OP_ADJUST_TIMESTAMP_FREQ);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_freq);
|
||||
|
||||
struct config_edma_ring_blks_param {
|
||||
unsigned int ering;
|
||||
unsigned int max_blks;
|
||||
|
@ -520,6 +500,24 @@ int gxio_mpipe_config_edma_ring_blks(gxio_mpipe_context_t * context,
|
|||
|
||||
EXPORT_SYMBOL(gxio_mpipe_config_edma_ring_blks);
|
||||
|
||||
struct adjust_timestamp_freq_param {
|
||||
int32_t ppb;
|
||||
};
|
||||
|
||||
int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t *context, int32_t ppb)
|
||||
{
|
||||
struct adjust_timestamp_freq_param temp;
|
||||
struct adjust_timestamp_freq_param *params = &temp;
|
||||
|
||||
params->ppb = ppb;
|
||||
|
||||
return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
|
||||
sizeof(*params),
|
||||
GXIO_MPIPE_OP_ADJUST_TIMESTAMP_FREQ);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_freq);
|
||||
|
||||
struct arm_pollfd_param {
|
||||
union iorpc_pollfd pollfd;
|
||||
};
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
/* This file is machine-generated; DO NOT EDIT! */
|
||||
#include "gxio/iorpc_mpipe_info.h"
|
||||
|
||||
|
||||
struct instance_aux_param {
|
||||
_gxio_mpipe_link_name_t name;
|
||||
};
|
||||
|
|
|
@ -176,7 +176,18 @@ typedef union
|
|||
*/
|
||||
uint_reg_t stack_idx : 5;
|
||||
/* Reserved. */
|
||||
uint_reg_t __reserved_2 : 5;
|
||||
uint_reg_t __reserved_2 : 3;
|
||||
/*
|
||||
* Instance ID. For devices that support automatic buffer return between
|
||||
* mPIPE instances, this field indicates the buffer owner. If the INST
|
||||
* field does not match the mPIPE's instance number when a packet is
|
||||
* egressed, buffers with HWB set will be returned to the other mPIPE
|
||||
* instance. Note that not all devices support multi-mPIPE buffer
|
||||
* return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
|
||||
* whether the INST field in the buffer descriptor is populated by iDMA
|
||||
* hardware. This field is ignored on writes.
|
||||
*/
|
||||
uint_reg_t inst : 2;
|
||||
/*
|
||||
* Reads as one to indicate that this is a hardware managed buffer.
|
||||
* Ignored on writes since all buffers on a given stack are the same size.
|
||||
|
@ -205,7 +216,8 @@ typedef union
|
|||
uint_reg_t c : 2;
|
||||
uint_reg_t size : 3;
|
||||
uint_reg_t hwb : 1;
|
||||
uint_reg_t __reserved_2 : 5;
|
||||
uint_reg_t inst : 2;
|
||||
uint_reg_t __reserved_2 : 3;
|
||||
uint_reg_t stack_idx : 5;
|
||||
uint_reg_t __reserved_1 : 6;
|
||||
int_reg_t va : 35;
|
||||
|
@ -231,9 +243,9 @@ typedef union
|
|||
/* Reserved. */
|
||||
uint_reg_t __reserved_0 : 3;
|
||||
/* eDMA ring being accessed */
|
||||
uint_reg_t ring : 5;
|
||||
uint_reg_t ring : 6;
|
||||
/* Reserved. */
|
||||
uint_reg_t __reserved_1 : 18;
|
||||
uint_reg_t __reserved_1 : 17;
|
||||
/*
|
||||
* This field of the address selects the region (address space) to be
|
||||
* accessed. For the egress DMA post region, this field must be 5.
|
||||
|
@ -250,8 +262,8 @@ typedef union
|
|||
uint_reg_t svc_dom : 5;
|
||||
uint_reg_t __reserved_2 : 6;
|
||||
uint_reg_t region : 3;
|
||||
uint_reg_t __reserved_1 : 18;
|
||||
uint_reg_t ring : 5;
|
||||
uint_reg_t __reserved_1 : 17;
|
||||
uint_reg_t ring : 6;
|
||||
uint_reg_t __reserved_0 : 3;
|
||||
#endif
|
||||
};
|
||||
|
|
|
@ -16,13 +16,13 @@
|
|||
#ifndef __ARCH_MPIPE_CONSTANTS_H__
|
||||
#define __ARCH_MPIPE_CONSTANTS_H__
|
||||
|
||||
#define MPIPE_NUM_CLASSIFIERS 10
|
||||
#define MPIPE_NUM_CLASSIFIERS 16
|
||||
#define MPIPE_CLS_MHZ 1200
|
||||
|
||||
#define MPIPE_NUM_EDMA_RINGS 32
|
||||
#define MPIPE_NUM_EDMA_RINGS 64
|
||||
|
||||
#define MPIPE_NUM_SGMII_MACS 16
|
||||
#define MPIPE_NUM_XAUI_MACS 4
|
||||
#define MPIPE_NUM_XAUI_MACS 16
|
||||
#define MPIPE_NUM_LOOPBACK_CHANNELS 4
|
||||
#define MPIPE_NUM_NON_LB_CHANNELS 28
|
||||
|
||||
|
|
|
@ -44,8 +44,14 @@ typedef union
|
|||
* descriptors toggles each time the ring tail pointer wraps.
|
||||
*/
|
||||
uint_reg_t gen : 1;
|
||||
/**
|
||||
* For devices with EDMA reorder support, this field allows the
|
||||
* descriptor to select the egress FIFO. The associated DMA ring must
|
||||
* have ALLOW_EFIFO_SEL enabled.
|
||||
*/
|
||||
uint_reg_t efifo_sel : 6;
|
||||
/** Reserved. Must be zero. */
|
||||
uint_reg_t r0 : 7;
|
||||
uint_reg_t r0 : 1;
|
||||
/** Checksum generation enabled for this transfer. */
|
||||
uint_reg_t csum : 1;
|
||||
/**
|
||||
|
@ -110,7 +116,8 @@ typedef union
|
|||
uint_reg_t notif : 1;
|
||||
uint_reg_t ns : 1;
|
||||
uint_reg_t csum : 1;
|
||||
uint_reg_t r0 : 7;
|
||||
uint_reg_t r0 : 1;
|
||||
uint_reg_t efifo_sel : 6;
|
||||
uint_reg_t gen : 1;
|
||||
#endif
|
||||
|
||||
|
@ -126,14 +133,16 @@ typedef union
|
|||
/** Reserved. */
|
||||
uint_reg_t __reserved_1 : 3;
|
||||
/**
|
||||
* Instance ID. For devices that support more than one mPIPE instance,
|
||||
* this field indicates the buffer owner. If the INST field does not
|
||||
* match the mPIPE's instance number when a packet is egressed, buffers
|
||||
* with HWB set will be returned to the other mPIPE instance.
|
||||
* Instance ID. For devices that support automatic buffer return between
|
||||
* mPIPE instances, this field indicates the buffer owner. If the INST
|
||||
* field does not match the mPIPE's instance number when a packet is
|
||||
* egressed, buffers with HWB set will be returned to the other mPIPE
|
||||
* instance. Note that not all devices support multi-mPIPE buffer
|
||||
* return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
|
||||
* whether the INST field in the buffer descriptor is populated by iDMA
|
||||
* hardware.
|
||||
*/
|
||||
uint_reg_t inst : 1;
|
||||
/** Reserved. */
|
||||
uint_reg_t __reserved_2 : 1;
|
||||
uint_reg_t inst : 2;
|
||||
/**
|
||||
* Always set to one by hardware in iDMA packet descriptors. For eDMA,
|
||||
* indicates whether the buffer will be released to the buffer stack
|
||||
|
@ -166,8 +175,7 @@ typedef union
|
|||
uint_reg_t c : 2;
|
||||
uint_reg_t size : 3;
|
||||
uint_reg_t hwb : 1;
|
||||
uint_reg_t __reserved_2 : 1;
|
||||
uint_reg_t inst : 1;
|
||||
uint_reg_t inst : 2;
|
||||
uint_reg_t __reserved_1 : 3;
|
||||
uint_reg_t stack_idx : 5;
|
||||
uint_reg_t __reserved_0 : 6;
|
||||
|
@ -408,7 +416,10 @@ typedef union
|
|||
/**
|
||||
* Sequence number applied when packet is distributed. Classifier
|
||||
* selects which sequence number is to be applied by writing the 13-bit
|
||||
* SQN-selector into this field.
|
||||
* SQN-selector into this field. For devices that support EXT_SQN (as
|
||||
* indicated in IDMA_INFO.EXT_SQN_SUPPORT), the GP_SQN can be extended to
|
||||
* 32-bits via the IDMA_CTL.EXT_SQN register. In this case the
|
||||
* PACKET_SQN will be reduced to 32 bits.
|
||||
*/
|
||||
uint_reg_t gp_sqn : 16;
|
||||
/**
|
||||
|
@ -451,14 +462,16 @@ typedef union
|
|||
/** Reserved. */
|
||||
uint_reg_t __reserved_5 : 3;
|
||||
/**
|
||||
* Instance ID. For devices that support more than one mPIPE instance,
|
||||
* this field indicates the buffer owner. If the INST field does not
|
||||
* match the mPIPE's instance number when a packet is egressed, buffers
|
||||
* with HWB set will be returned to the other mPIPE instance.
|
||||
* Instance ID. For devices that support automatic buffer return between
|
||||
* mPIPE instances, this field indicates the buffer owner. If the INST
|
||||
* field does not match the mPIPE's instance number when a packet is
|
||||
* egressed, buffers with HWB set will be returned to the other mPIPE
|
||||
* instance. Note that not all devices support multi-mPIPE buffer
|
||||
* return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
|
||||
* whether the INST field in the buffer descriptor is populated by iDMA
|
||||
* hardware.
|
||||
*/
|
||||
uint_reg_t inst : 1;
|
||||
/** Reserved. */
|
||||
uint_reg_t __reserved_6 : 1;
|
||||
uint_reg_t inst : 2;
|
||||
/**
|
||||
* Always set to one by hardware in iDMA packet descriptors. For eDMA,
|
||||
* indicates whether the buffer will be released to the buffer stack
|
||||
|
@ -491,8 +504,7 @@ typedef union
|
|||
uint_reg_t c : 2;
|
||||
uint_reg_t size : 3;
|
||||
uint_reg_t hwb : 1;
|
||||
uint_reg_t __reserved_6 : 1;
|
||||
uint_reg_t inst : 1;
|
||||
uint_reg_t inst : 2;
|
||||
uint_reg_t __reserved_5 : 3;
|
||||
uint_reg_t stack_idx : 5;
|
||||
uint_reg_t __reserved_4 : 6;
|
||||
|
|
|
@ -16,21 +16,21 @@
|
|||
#ifndef __ARCH_TRIO_CONSTANTS_H__
|
||||
#define __ARCH_TRIO_CONSTANTS_H__
|
||||
|
||||
#define TRIO_NUM_ASIDS 16
|
||||
#define TRIO_NUM_ASIDS 32
|
||||
#define TRIO_NUM_TLBS_PER_ASID 16
|
||||
|
||||
#define TRIO_NUM_TPIO_REGIONS 8
|
||||
#define TRIO_LOG2_NUM_TPIO_REGIONS 3
|
||||
|
||||
#define TRIO_NUM_MAP_MEM_REGIONS 16
|
||||
#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 4
|
||||
#define TRIO_NUM_MAP_MEM_REGIONS 32
|
||||
#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 5
|
||||
#define TRIO_NUM_MAP_SQ_REGIONS 8
|
||||
#define TRIO_LOG2_NUM_MAP_SQ_REGIONS 3
|
||||
|
||||
#define TRIO_LOG2_NUM_SQ_FIFO_ENTRIES 6
|
||||
|
||||
#define TRIO_NUM_PUSH_DMA_RINGS 32
|
||||
#define TRIO_NUM_PUSH_DMA_RINGS 64
|
||||
|
||||
#define TRIO_NUM_PULL_DMA_RINGS 32
|
||||
#define TRIO_NUM_PULL_DMA_RINGS 64
|
||||
|
||||
#endif /* __ARCH_TRIO_CONSTANTS_H__ */
|
||||
|
|
|
@ -182,10 +182,9 @@ static inline __attribute_const__ int get_order(unsigned long size)
|
|||
|
||||
#define PAGE_OFFSET (-(_AC(1, UL) << (MAX_VA_WIDTH - 1)))
|
||||
#define KERNEL_HIGH_VADDR _AC(0xfffffff800000000, UL) /* high 32GB */
|
||||
#define FIXADDR_BASE (KERNEL_HIGH_VADDR - 0x400000000) /* 4 GB */
|
||||
#define FIXADDR_TOP (KERNEL_HIGH_VADDR - 0x300000000) /* 4 GB */
|
||||
#define FIXADDR_BASE (KERNEL_HIGH_VADDR - 0x300000000) /* 4 GB */
|
||||
#define FIXADDR_TOP (KERNEL_HIGH_VADDR - 0x200000000) /* 4 GB */
|
||||
#define _VMALLOC_START FIXADDR_TOP
|
||||
#define HUGE_VMAP_BASE (KERNEL_HIGH_VADDR - 0x200000000) /* 4 GB */
|
||||
#define MEM_SV_START (KERNEL_HIGH_VADDR - 0x100000000) /* 256 MB */
|
||||
#define MEM_MODULE_START (MEM_SV_START + (256*1024*1024)) /* 256 MB */
|
||||
#define MEM_MODULE_END (MEM_MODULE_START + (256*1024*1024))
|
||||
|
|
|
@ -55,17 +55,9 @@
|
|||
#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE*LAST_PKMAP) & PGDIR_MASK)
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
# define __VMAPPING_END (PKMAP_BASE & ~(HPAGE_SIZE-1))
|
||||
# define _VMALLOC_END (PKMAP_BASE & ~(HPAGE_SIZE-1))
|
||||
#else
|
||||
# define __VMAPPING_END (FIXADDR_START & ~(HPAGE_SIZE-1))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HUGEVMAP
|
||||
#define HUGE_VMAP_END __VMAPPING_END
|
||||
#define HUGE_VMAP_BASE (HUGE_VMAP_END - CONFIG_NR_HUGE_VMAPS * HPAGE_SIZE)
|
||||
#define _VMALLOC_END HUGE_VMAP_BASE
|
||||
#else
|
||||
#define _VMALLOC_END __VMAPPING_END
|
||||
# define _VMALLOC_END (FIXADDR_START & ~(HPAGE_SIZE-1))
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -52,12 +52,10 @@
|
|||
* memory allocation code). The vmalloc code puts in an internal
|
||||
* guard page between each allocation.
|
||||
*/
|
||||
#define _VMALLOC_END HUGE_VMAP_BASE
|
||||
#define _VMALLOC_END MEM_SV_START
|
||||
#define VMALLOC_END _VMALLOC_END
|
||||
#define VMALLOC_START _VMALLOC_START
|
||||
|
||||
#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* We have no pud since we are a three-level page table. */
|
||||
|
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* Atomically access user memory, but use MMU to avoid propagating
|
||||
* kernel exceptions.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/futex.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* Provide a set of atomic memory operations supporting <asm/futex.h>.
|
||||
*
|
||||
* r0: user address to manipulate
|
||||
* r1: new value to write, or for cmpxchg, old value to compare against
|
||||
* r2: (cmpxchg only) new value to write
|
||||
*
|
||||
* Return __get_user struct, r0 with value, r1 with error.
|
||||
*/
|
||||
#define FUTEX_OP(name, ...) \
|
||||
STD_ENTRY(futex_##name) \
|
||||
__VA_ARGS__; \
|
||||
{ \
|
||||
move r1, zero; \
|
||||
jrp lr \
|
||||
}; \
|
||||
STD_ENDPROC(futex_##name); \
|
||||
.pushsection __ex_table,"a"; \
|
||||
.quad 1b, get_user_fault; \
|
||||
.popsection
|
||||
|
||||
.pushsection .fixup,"ax"
|
||||
get_user_fault:
|
||||
{ movei r1, -EFAULT; jrp lr }
|
||||
ENDPROC(get_user_fault)
|
||||
.popsection
|
||||
|
||||
FUTEX_OP(cmpxchg, mtspr CMPEXCH_VALUE, r1; 1: cmpexch4 r0, r0, r2)
|
||||
FUTEX_OP(set, 1: exch4 r0, r0, r1)
|
||||
FUTEX_OP(add, 1: fetchadd4 r0, r0, r1)
|
||||
FUTEX_OP(or, 1: fetchor4 r0, r0, r1)
|
||||
FUTEX_OP(andn, nor r1, r1, zero; 1: fetchand4 r0, r0, r1)
|
|
@ -1268,8 +1268,7 @@ static void __init validate_va(void)
|
|||
if ((long)VMALLOC_START >= 0)
|
||||
early_panic(
|
||||
"Linux VMALLOC region below the 2GB line (%#lx)!\n"
|
||||
"Reconfigure the kernel with fewer NR_HUGE_VMAPS\n"
|
||||
"or smaller VMALLOC_RESERVE.\n",
|
||||
"Reconfigure the kernel with smaller VMALLOC_RESERVE.\n",
|
||||
VMALLOC_START);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -551,8 +551,8 @@ static tilegx_bundle_bits jit_x1_bnezt(int ra, int broff)
|
|||
/*
|
||||
* This function generates unalign fixup JIT.
|
||||
*
|
||||
* We fist find unalign load/store instruction's destination, source
|
||||
* reguisters: ra, rb and rd. and 3 scratch registers by calling
|
||||
* We first find unalign load/store instruction's destination, source
|
||||
* registers: ra, rb and rd. and 3 scratch registers by calling
|
||||
* find_regs(...). 3 scratch clobbers should not alias with any register
|
||||
* used in the fault bundle. Then analyze the fault bundle to determine
|
||||
* if it's a load or store, operand width, branch or address increment etc.
|
||||
|
|
|
@ -149,8 +149,6 @@ static inline int vmalloc_fault(pgd_t *pgd, unsigned long address)
|
|||
pmd_k = vmalloc_sync_one(pgd, address);
|
||||
if (!pmd_k)
|
||||
return -1;
|
||||
if (pmd_huge(*pmd_k))
|
||||
return 0; /* support TILE huge_vmap() API */
|
||||
pte_k = pte_offset_kernel(pmd_k, address);
|
||||
if (!pte_present(*pte_k))
|
||||
return -1;
|
||||
|
|
|
@ -827,10 +827,6 @@ void __init mem_init(void)
|
|||
FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
|
||||
printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
|
||||
PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
|
||||
#endif
|
||||
#ifdef CONFIG_HUGEVMAP
|
||||
printk(KERN_DEBUG " HUGEMAP %#lx - %#lx\n",
|
||||
HUGE_VMAP_BASE, HUGE_VMAP_END - 1);
|
||||
#endif
|
||||
printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
|
||||
_VMALLOC_START, _VMALLOC_END - 1);
|
||||
|
|
|
@ -127,8 +127,7 @@ void shatter_huge_page(unsigned long addr)
|
|||
}
|
||||
|
||||
/* Shatter the huge page into the preallocated L2 page table. */
|
||||
pmd_populate_kernel(&init_mm, pmd,
|
||||
get_prealloc_pte(pte_pfn(*(pte_t *)pmd)));
|
||||
pmd_populate_kernel(&init_mm, pmd, get_prealloc_pte(pmd_pfn(*pmd)));
|
||||
|
||||
#ifdef __PAGETABLE_PMD_FOLDED
|
||||
/* Walk every pgd on the system and update the pmd there. */
|
||||
|
|
|
@ -481,11 +481,12 @@ config X86_INTEL_LPSS
|
|||
bool "Intel Low Power Subsystem Support"
|
||||
depends on ACPI
|
||||
select COMMON_CLK
|
||||
select PINCTRL
|
||||
---help---
|
||||
Select to build support for Intel Low Power Subsystem such as
|
||||
found on Intel Lynxpoint PCH. Selecting this option enables
|
||||
things like clock tree (common clock framework) which are needed
|
||||
by the LPSS peripheral drivers.
|
||||
things like clock tree (common clock framework) and pincontrol
|
||||
which are needed by the LPSS peripheral drivers.
|
||||
|
||||
config X86_RDC321X
|
||||
bool "RDC R-321x SoC"
|
||||
|
|
|
@ -899,8 +899,8 @@ static __initconst const u64 atom_hw_cache_event_ids
|
|||
static struct extra_reg intel_slm_extra_regs[] __read_mostly =
|
||||
{
|
||||
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
|
||||
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffff, RSP_0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffff, RSP_1),
|
||||
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
|
||||
INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
|
||||
EVENT_EXTRA_END
|
||||
};
|
||||
|
||||
|
|
|
@ -584,6 +584,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
|
|||
INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
|
||||
INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
|
||||
INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
|
||||
INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
|
||||
INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
|
||||
EVENT_CONSTRAINT_END
|
||||
};
|
||||
|
|
|
@ -487,21 +487,6 @@ ENDPROC(native_usergs_sysret64)
|
|||
TRACE_IRQS_OFF
|
||||
.endm
|
||||
|
||||
ENTRY(save_rest)
|
||||
PARTIAL_FRAME 1 (REST_SKIP+8)
|
||||
movq 5*8+16(%rsp), %r11 /* save return address */
|
||||
movq_cfi rbx, RBX+16
|
||||
movq_cfi rbp, RBP+16
|
||||
movq_cfi r12, R12+16
|
||||
movq_cfi r13, R13+16
|
||||
movq_cfi r14, R14+16
|
||||
movq_cfi r15, R15+16
|
||||
movq %r11, 8(%rsp) /* return address */
|
||||
FIXUP_TOP_OF_STACK %r11, 16
|
||||
ret
|
||||
CFI_ENDPROC
|
||||
END(save_rest)
|
||||
|
||||
/* save complete stack frame */
|
||||
.pushsection .kprobes.text, "ax"
|
||||
ENTRY(save_paranoid)
|
||||
|
|
|
@ -653,6 +653,7 @@ static void announce_cpu(int cpu, int apicid)
|
|||
{
|
||||
static int current_node = -1;
|
||||
int node = early_cpu_to_node(cpu);
|
||||
int max_cpu_present = find_last_bit(cpumask_bits(cpu_present_mask), NR_CPUS);
|
||||
|
||||
if (system_state == SYSTEM_BOOTING) {
|
||||
if (node != current_node) {
|
||||
|
@ -661,7 +662,7 @@ static void announce_cpu(int cpu, int apicid)
|
|||
current_node = node;
|
||||
pr_info("Booting Node %3d, Processors ", node);
|
||||
}
|
||||
pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : "");
|
||||
pr_cont(" #%4d%s", cpu, cpu == max_cpu_present ? " OK\n" : "");
|
||||
return;
|
||||
} else
|
||||
pr_info("Booting Node %d Processor %d APIC 0x%x\n",
|
||||
|
|
|
@ -2025,6 +2025,17 @@ static int em_ret_far(struct x86_emulate_ctxt *ctxt)
|
|||
return rc;
|
||||
}
|
||||
|
||||
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = em_ret_far(ctxt);
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
return rc;
|
||||
rsp_increment(ctxt, ctxt->src.val);
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
/* Save real source value, then compare EAX against destination. */
|
||||
|
@ -3763,7 +3774,8 @@ static const struct opcode opcode_table[256] = {
|
|||
G(ByteOp, group11), G(0, group11),
|
||||
/* 0xC8 - 0xCF */
|
||||
I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
|
||||
N, I(ImplicitOps | Stack, em_ret_far),
|
||||
I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
|
||||
I(ImplicitOps | Stack, em_ret_far),
|
||||
D(ImplicitOps), DI(SrcImmByte, intn),
|
||||
D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
|
||||
/* 0xD0 - 0xD7 */
|
||||
|
|
|
@ -99,6 +99,7 @@ struct guest_walker {
|
|||
pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
|
||||
gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
|
||||
pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
|
||||
bool pte_writable[PT_MAX_FULL_LEVELS];
|
||||
unsigned pt_access;
|
||||
unsigned pte_access;
|
||||
gfn_t gfn;
|
||||
|
@ -235,6 +236,22 @@ static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
|
|||
if (pte == orig_pte)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* If the slot is read-only, simply do not process the accessed
|
||||
* and dirty bits. This is the correct thing to do if the slot
|
||||
* is ROM, and page tables in read-as-ROM/write-as-MMIO slots
|
||||
* are only supported if the accessed and dirty bits are already
|
||||
* set in the ROM (so that MMIO writes are never needed).
|
||||
*
|
||||
* Note that NPT does not allow this at all and faults, since
|
||||
* it always wants nested page table entries for the guest
|
||||
* page tables to be writable. And EPT works but will simply
|
||||
* overwrite the read-only memory to set the accessed and dirty
|
||||
* bits.
|
||||
*/
|
||||
if (unlikely(!walker->pte_writable[level - 1]))
|
||||
continue;
|
||||
|
||||
ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
@ -309,7 +326,8 @@ retry_walk:
|
|||
goto error;
|
||||
real_gfn = gpa_to_gfn(real_gfn);
|
||||
|
||||
host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
|
||||
host_addr = gfn_to_hva_prot(vcpu->kvm, real_gfn,
|
||||
&walker->pte_writable[walker->level - 1]);
|
||||
if (unlikely(kvm_is_error_hva(host_addr)))
|
||||
goto error;
|
||||
|
||||
|
|
|
@ -5339,6 +5339,15 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* EPT violation happened while executing iret from NMI,
|
||||
* "blocked by NMI" bit has to be set before next VM entry.
|
||||
* There are errata that may cause this bit to not be set:
|
||||
* AAK134, BY25.
|
||||
*/
|
||||
if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
|
||||
vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
|
||||
|
||||
gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
|
||||
trace_kvm_page_fault(gpa, exit_qualification);
|
||||
|
||||
|
@ -7766,6 +7775,10 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
|
|||
vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
|
||||
vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
|
||||
vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
|
||||
__clear_bit(VCPU_EXREG_PDPTR,
|
||||
(unsigned long *)&vcpu->arch.regs_avail);
|
||||
__clear_bit(VCPU_EXREG_PDPTR,
|
||||
(unsigned long *)&vcpu->arch.regs_dirty);
|
||||
}
|
||||
|
||||
kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
|
||||
|
|
|
@ -235,8 +235,13 @@ static struct blkcg_gq *blkg_create(struct blkcg *blkcg,
|
|||
blkg->online = true;
|
||||
spin_unlock(&blkcg->lock);
|
||||
|
||||
if (!ret)
|
||||
if (!ret) {
|
||||
if (blkcg == &blkcg_root) {
|
||||
q->root_blkg = blkg;
|
||||
q->root_rl.blkg = blkg;
|
||||
}
|
||||
return blkg;
|
||||
}
|
||||
|
||||
/* @blkg failed fully initialized, use the usual release path */
|
||||
blkg_put(blkg);
|
||||
|
@ -334,6 +339,15 @@ static void blkg_destroy(struct blkcg_gq *blkg)
|
|||
if (rcu_dereference_raw(blkcg->blkg_hint) == blkg)
|
||||
rcu_assign_pointer(blkcg->blkg_hint, NULL);
|
||||
|
||||
/*
|
||||
* If root blkg is destroyed. Just clear the pointer since root_rl
|
||||
* does not take reference on root blkg.
|
||||
*/
|
||||
if (blkcg == &blkcg_root) {
|
||||
blkg->q->root_blkg = NULL;
|
||||
blkg->q->root_rl.blkg = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Put the reference taken at the time of creation so that when all
|
||||
* queues are gone, group can be destroyed.
|
||||
|
@ -360,13 +374,6 @@ static void blkg_destroy_all(struct request_queue *q)
|
|||
blkg_destroy(blkg);
|
||||
spin_unlock(&blkcg->lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* root blkg is destroyed. Just clear the pointer since
|
||||
* root_rl does not take reference on root blkg.
|
||||
*/
|
||||
q->root_blkg = NULL;
|
||||
q->root_rl.blkg = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -970,8 +977,6 @@ int blkcg_activate_policy(struct request_queue *q,
|
|||
ret = PTR_ERR(blkg);
|
||||
goto out_unlock;
|
||||
}
|
||||
q->root_blkg = blkg;
|
||||
q->root_rl.blkg = blkg;
|
||||
|
||||
list_for_each_entry(blkg, &q->blkg_list, q_node)
|
||||
cnt++;
|
||||
|
|
|
@ -1549,11 +1549,9 @@ get_rq:
|
|||
if (plug) {
|
||||
/*
|
||||
* If this is the first request added after a plug, fire
|
||||
* of a plug trace. If others have been added before, check
|
||||
* if we have multiple devices in this plug. If so, make a
|
||||
* note to sort the list before dispatch.
|
||||
* of a plug trace.
|
||||
*/
|
||||
if (list_empty(&plug->list))
|
||||
if (!request_count)
|
||||
trace_block_plug(q);
|
||||
else {
|
||||
if (request_count >= BLK_MAX_REQUEST_COUNT) {
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue