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clk: renesas: mstp: Support 8-bit registers for r7s72100 

The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.

Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chris Brandt 2016-12-15 12:00:27 -05:00 committed by Stephen Boyd
parent 2aab7a2055
commit e2a33c34dd
1 changed files with 22 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/clk/renesas/clk-mstp.c
View File

@ -37,12 +37,14 @@
* @smstpcr: module stop control register * @smstpcr: module stop control register
* @mstpsr: module stop status register (optional) * @mstpsr: module stop status register (optional)
* @lock: protects writes to SMSTPCR * @lock: protects writes to SMSTPCR
* @width_8bit: registers are 8-bit, not 32-bit
*/ */
struct mstp_clock_group { struct mstp_clock_group {
struct clk_onecell_data data; struct clk_onecell_data data;
void __iomem *smstpcr; void __iomem *smstpcr;
void __iomem *mstpsr; void __iomem *mstpsr;
spinlock_t lock; spinlock_t lock;
bool width_8bit;
}; };
/** /**
@ -59,6 +61,18 @@ struct mstp_clock {
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
u32 __iomem *reg)
{
return group->width_8bit ? readb(reg) : clk_readl(reg);
}
static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
u32 __iomem *reg)
{
group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
}
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
{ {
struct mstp_clock *clock = to_mstp_clock(hw); struct mstp_clock *clock = to_mstp_clock(hw);
@ -70,12 +84,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
spin_lock_irqsave(&group->lock, flags); spin_lock_irqsave(&group->lock, flags);
value = clk_readl(group->smstpcr); value = cpg_mstp_read(group, group->smstpcr);
if (enable) if (enable)
value &= ~bitmask; value &= ~bitmask;
else else
value |= bitmask; value |= bitmask;
clk_writel(value, group->smstpcr); cpg_mstp_write(group, value, group->smstpcr);
spin_unlock_irqrestore(&group->lock, flags); spin_unlock_irqrestore(&group->lock, flags);
@ -83,7 +97,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
return 0; return 0;
for (i = 1000; i > 0; --i) { for (i = 1000; i > 0; --i) {
if (!(clk_readl(group->mstpsr) & bitmask)) if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
break; break;
cpu_relax(); cpu_relax();
} }
@ -114,9 +128,9 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
u32 value; u32 value;
if (group->mstpsr) if (group->mstpsr)
value = clk_readl(group->mstpsr); value = cpg_mstp_read(group, group->mstpsr);
else else
value = clk_readl(group->smstpcr); value = cpg_mstp_read(group, group->smstpcr);
return !(value & BIT(clock->bit_index)); return !(value & BIT(clock->bit_index));
} }
@ -188,6 +202,9 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
return; return;
} }
if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
group->width_8bit = true;
for (i = 0; i < MSTP_MAX_CLOCKS; ++i) for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
clks[i] = ERR_PTR(-ENOENT); clks[i] = ERR_PTR(-ENOENT);