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dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver 

New atmel DMA controller known as XDMAC, introduced with SAMA5D4
devices.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Ludovic Desroches 2014-10-22 17:22:18 +02:00 committed by Vinod Koul
parent 0df1f2487d
commit e1f7c9eee7
4 changed files with 1543 additions and 0 deletions
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7
drivers/dma/Kconfig
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@ -107,6 +107,13 @@ config AT_HDMAC
help help
Support the Atmel AHB DMA controller. Support the Atmel AHB DMA controller.
config AT_XDMAC
tristate "Atmel XDMA support"
depends on (ARCH_AT91 || COMPILE_TEST)
select DMA_ENGINE
help
Support the Atmel XDMA controller.
config FSL_DMA config FSL_DMA
tristate "Freescale Elo series DMA support" tristate "Freescale Elo series DMA support"
depends on FSL_SOC depends on FSL_SOC

1
drivers/dma/Makefile
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@ -16,6 +16,7 @@ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
obj-$(CONFIG_MV_XOR) += mv_xor.o obj-$(CONFIG_MV_XOR) += mv_xor.o
obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_AT_HDMAC) += at_hdmac.o obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
obj-$(CONFIG_MX3_IPU) += ipu/ obj-$(CONFIG_MX3_IPU) += ipu/
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_SH_DMAE_BASE) += sh/ obj-$(CONFIG_SH_DMAE_BASE) += sh/

1510
drivers/dma/at_xdmac.c Normal file
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File diff suppressed because it is too large Load Diff

25
include/dt-bindings/dma/at91.h
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@ -9,6 +9,8 @@
#ifndef __DT_BINDINGS_AT91_DMA_H__ #ifndef __DT_BINDINGS_AT91_DMA_H__
#define __DT_BINDINGS_AT91_DMA_H__ #define __DT_BINDINGS_AT91_DMA_H__
/* ---------- HDMAC ---------- */
/* /*
* Source and/or destination peripheral ID * Source and/or destination peripheral ID
*/ */
@ -24,4 +26,27 @@
#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
/* ---------- XDMAC ---------- */
#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
<< AT91_XDMAC_DT_MEM_IF_OFFSET)
#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
& AT91_XDMAC_DT_MEM_IF_MASK)
#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
<< AT91_XDMAC_DT_PER_IF_OFFSET)
#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
& AT91_XDMAC_DT_PER_IF_MASK)
#define AT91_XDMAC_DT_PERID_MASK (0x7f)
#define AT91_XDMAC_DT_PERID_OFFSET (24)
#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
<< AT91_XDMAC_DT_PERID_OFFSET)
#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
& AT91_XDMAC_DT_PERID_MASK)
#endif /* __DT_BINDINGS_AT91_DMA_H__ */ #endif /* __DT_BINDINGS_AT91_DMA_H__ */