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dt-bindings: mmc: mmci: add delay block base register for sdmmc 

To support the sdr104 mode, the sdmmc variant has a hardware delay block to
manage the clock phase when sampling data received by the card.

This patch adds a second base register (optional) for sdmmc delay block.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200128090636.13689-6-ludovic.barre@st.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ludovic Barre 2020-01-28 10:06:32 +01:00 committed by Ulf Hansson
parent 31b963e194
commit e19c33dbfe
1 changed files with 2 additions and 0 deletions
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Documentation/devicetree/bindings/mmc/mmci.txt
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@ -28,6 +28,8 @@ specific for ux500 variant:
- st,sig-pin-fbclk : feedback clock signal pin used.
specific for sdmmc variant:
- reg : a second base register may be defined if a delay
block is present and used for tuning.
- st,sig-dir : signal direction polarity used for cmd, dat0 dat123.
- st,neg-edge : data & command phase relation, generated on
sd clock falling edge.