i2c: Add Renesas RZ/V2M controller
Yet another i2c controller from Renesas that is found on the RZ/V2M (r9a09g011) SoC. It can support only 100kHz and 400KHz operation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> [wsa: removed superfluous class type and renamed a function] Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Phil Edworthy
Wolfram Sang
parent
ba7a4d15e2
commit
e0ca796a15
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@ -996,6 +996,16 @@ config I2C_RK3X
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This driver can also be built as a module. If so, the module will
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be called i2c-rk3x.
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config I2C_RZV2M
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tristate "Renesas RZ/V2M adapter"
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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If you say yes to this option, support will be included for the
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Renesas RZ/V2M I2C interface.
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This driver can also be built as a module. If so, the module
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will be called i2c-rzv2m.
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config I2C_S3C2410
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tristate "S3C/Exynos I2C Driver"
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depends on ARCH_EXYNOS || ARCH_S3C24XX || ARCH_S3C64XX || \
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@ -102,6 +102,7 @@ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
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obj-$(CONFIG_I2C_QUP) += i2c-qup.o
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obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
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obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
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obj-$(CONFIG_I2C_RZV2M) += i2c-rzv2m.o
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obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
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obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
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obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
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@ -0,0 +1,532 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Renesas RZ/V2M I2C unit
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*
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* Copyright (C) 2016-2022 Renesas Electronics Corporation
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/i2c.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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/* Register offsets */
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#define IICB0DAT 0x00 /* Data Register */
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#define IICB0CTL0 0x08 /* Control Register 0 */
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#define IICB0TRG 0x0C /* Trigger Register */
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#define IICB0STR0 0x10 /* Status Register 0 */
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#define IICB0CTL1 0x20 /* Control Register 1 */
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#define IICB0WL 0x24 /* Low Level Width Setting Reg */
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#define IICB0WH 0x28 /* How Level Width Setting Reg */
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/* IICB0CTL0 */
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#define IICB0IICE BIT(7) /* I2C Enable */
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#define IICB0SLWT BIT(1) /* Interrupt Request Timing */
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#define IICB0SLAC BIT(0) /* Acknowledge */
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/* IICB0TRG */
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#define IICB0WRET BIT(2) /* Quit Wait Trigger */
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#define IICB0STT BIT(1) /* Create Start Condition Trigger */
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#define IICB0SPT BIT(0) /* Create Stop Condition Trigger */
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/* IICB0STR0 */
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#define IICB0SSAC BIT(8) /* Ack Flag */
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#define IICB0SSBS BIT(6) /* Bus Flag */
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#define IICB0SSSP BIT(4) /* Stop Condition Flag */
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/* IICB0CTL1 */
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#define IICB0MDSC BIT(7) /* Bus Mode */
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#define IICB0SLSE BIT(1) /* Start condition output */
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#define bit_setl(addr, val) writel(readl(addr) | (val), (addr))
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#define bit_clrl(addr, val) writel(readl(addr) & ~(val), (addr))
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struct rzv2m_i2c_priv {
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void __iomem *base;
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struct i2c_adapter adap;
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struct clk *clk;
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int bus_mode;
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struct completion msg_tia_done;
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u32 iicb0wl;
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u32 iicb0wh;
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};
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enum bcr_index {
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RZV2M_I2C_100K = 0,
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RZV2M_I2C_400K,
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};
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struct bitrate_config {
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unsigned int percent_low;
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unsigned int min_hold_time_ns;
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};
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static const struct bitrate_config bitrate_configs[] = {
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[RZV2M_I2C_100K] = { 47, 3450 },
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[RZV2M_I2C_400K] = { 52, 900 },
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};
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static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
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{
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struct rzv2m_i2c_priv *priv = dev_id;
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complete(&priv->msg_tia_done);
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return IRQ_HANDLED;
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}
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/* Calculate IICB0WL and IICB0WH */
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static int rzv2m_i2c_clock_calculate(struct device *dev,
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struct rzv2m_i2c_priv *priv)
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{
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const struct bitrate_config *config;
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unsigned int hold_time_ns;
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unsigned int total_pclks;
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unsigned int trf_pclks;
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unsigned long pclk_hz;
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struct i2c_timings t;
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u32 trf_ns;
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i2c_parse_fw_timings(dev, &t, true);
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pclk_hz = clk_get_rate(priv->clk);
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total_pclks = pclk_hz / t.bus_freq_hz;
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trf_ns = t.scl_rise_ns + t.scl_fall_ns;
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trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
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/* Config setting */
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switch (t.bus_freq_hz) {
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case I2C_MAX_FAST_MODE_FREQ:
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priv->bus_mode = RZV2M_I2C_400K;
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break;
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case I2C_MAX_STANDARD_MODE_FREQ:
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priv->bus_mode = RZV2M_I2C_100K;
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break;
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default:
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dev_err(dev, "transfer speed is invalid\n");
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return -EINVAL;
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}
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config = &bitrate_configs[priv->bus_mode];
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/* IICB0WL = (percent_low / Transfer clock) x PCLK */
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priv->iicb0wl = total_pclks * config->percent_low / 100;
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if (priv->iicb0wl > (BIT(10) - 1))
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return -EINVAL;
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/* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
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priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
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if (priv->iicb0wh > (BIT(10) - 1))
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return -EINVAL;
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/*
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* Data hold time must be less than 0.9us in fast mode and
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* 3.45us in standard mode.
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* Data hold time = IICB0WL[9:2] / PCLK
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*/
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hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
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if (hold_time_ns > config->min_hold_time_ns) {
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dev_err(dev, "data hold time %dns is over %dns\n",
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hold_time_ns, config->min_hold_time_ns);
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return -EINVAL;
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}
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return 0;
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}
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static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
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{
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u32 i2c_ctl0;
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u32 i2c_ctl1;
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/* i2c disable */
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writel(0, priv->base + IICB0CTL0);
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/* IICB0CTL1 setting */
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i2c_ctl1 = IICB0SLSE;
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if (priv->bus_mode == RZV2M_I2C_400K)
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i2c_ctl1 |= IICB0MDSC;
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writel(i2c_ctl1, priv->base + IICB0CTL1);
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/* IICB0WL IICB0WH setting */
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writel(priv->iicb0wl, priv->base + IICB0WL);
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writel(priv->iicb0wh, priv->base + IICB0WH);
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/* i2c enable after setting */
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i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
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writel(i2c_ctl0, priv->base + IICB0CTL0);
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}
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static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
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{
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unsigned long time_left;
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reinit_completion(&priv->msg_tia_done);
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writel(data, priv->base + IICB0DAT);
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time_left = wait_for_completion_timeout(&priv->msg_tia_done,
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priv->adap.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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/* Confirm ACK */
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if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
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return -ENXIO;
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return 0;
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}
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static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
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bool last)
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{
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unsigned long time_left;
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u32 data_tmp;
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reinit_completion(&priv->msg_tia_done);
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/* Interrupt request timing : 8th clock */
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bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
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/* Exit the wait state */
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writel(IICB0WRET, priv->base + IICB0TRG);
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/* Wait for transaction */
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time_left = wait_for_completion_timeout(&priv->msg_tia_done,
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priv->adap.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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if (last) {
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/* Disable ACK */
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bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
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/* Read data*/
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data_tmp = readl(priv->base + IICB0DAT);
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/* Interrupt request timing : 9th clock */
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bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
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/* Exit the wait state */
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writel(IICB0WRET, priv->base + IICB0TRG);
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/* Wait for transaction */
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time_left = wait_for_completion_timeout(&priv->msg_tia_done,
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priv->adap.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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/* Enable ACK */
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bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
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} else {
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/* Read data */
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data_tmp = readl(priv->base + IICB0DAT);
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}
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*data = data_tmp;
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return 0;
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}
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static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
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unsigned int *count)
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{
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unsigned int i;
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int ret;
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for (i = 0; i < msg->len; i++) {
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ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
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if (ret < 0)
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return ret;
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}
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*count = i;
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return 0;
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}
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static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
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unsigned int *count)
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{
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unsigned int i;
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int ret;
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for (i = 0; i < msg->len; i++) {
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ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
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(msg->len - 1) == i);
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if (ret < 0)
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return ret;
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}
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*count = i;
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return 0;
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}
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static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
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struct i2c_msg *msg)
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{
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u32 addr;
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int ret;
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if (msg->flags & I2C_M_TEN) {
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/*
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* 10-bit address
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* addr_1: 5'b11110 | addr[9:8] | (R/nW)
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* addr_2: addr[7:0]
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*/
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addr = 0xf0 | ((msg->addr & GENMASK(9, 8)) >> 7);
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addr |= !!(msg->flags & I2C_M_RD);
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/* Send 1st address(extend code) */
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ret = rzv2m_i2c_write_with_ack(priv, addr);
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if (ret)
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return ret;
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/* Send 2nd address */
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ret = rzv2m_i2c_write_with_ack(priv, msg->addr & 0xff);
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} else {
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/* 7-bit address */
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addr = i2c_8bit_addr_from_msg(msg);
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ret = rzv2m_i2c_write_with_ack(priv, addr);
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}
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return ret;
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}
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static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
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{
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u32 value;
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/* Send stop condition */
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writel(IICB0SPT, priv->base + IICB0TRG);
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return readl_poll_timeout(priv->base + IICB0STR0,
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value, value & IICB0SSSP,
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100, jiffies_to_usecs(priv->adap.timeout));
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}
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static int rzv2m_i2c_master_xfer_msg(struct rzv2m_i2c_priv *priv,
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struct i2c_msg *msg, int stop)
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{
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unsigned int count = 0;
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int ret, read = !!(msg->flags & I2C_M_RD);
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/* Send start condition */
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writel(IICB0STT, priv->base + IICB0TRG);
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ret = rzv2m_i2c_send_address(priv, msg);
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if (!ret) {
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if (read)
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ret = rzv2m_i2c_receive(priv, msg, &count);
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else
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ret = rzv2m_i2c_send(priv, msg, &count);
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if (!ret && stop)
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ret = rzv2m_i2c_stop_condition(priv);
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}
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if (ret == -ENXIO)
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rzv2m_i2c_stop_condition(priv);
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else if (ret < 0)
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rzv2m_i2c_init(priv);
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else
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ret = count;
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return ret;
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}
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static int rzv2m_i2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
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struct device *dev = priv->adap.dev.parent;
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unsigned int i;
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int ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret < 0)
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return ret;
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if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
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ret = -EAGAIN;
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goto out;
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}
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/* I2C main transfer */
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for (i = 0; i < num; i++) {
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ret = rzv2m_i2c_master_xfer_msg(priv, &msgs[i], i == (num - 1));
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if (ret < 0)
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goto out;
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}
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ret = num;
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out:
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pm_runtime_mark_last_busy(dev);
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pm_runtime_put_autosuspend(dev);
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return ret;
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}
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static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
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I2C_FUNC_10BIT_ADDR;
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}
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static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
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.flags = I2C_AQ_NO_ZERO_LEN,
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};
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static struct i2c_algorithm rzv2m_i2c_algo = {
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.master_xfer = rzv2m_i2c_master_xfer,
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.functionality = rzv2m_i2c_func,
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};
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static int rzv2m_i2c_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzv2m_i2c_priv *priv;
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struct reset_control *rstc;
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struct i2c_adapter *adap;
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struct resource *res;
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int irq, ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(priv->base))
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||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(priv->clk))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
|
||||
|
||||
rstc = devm_reset_control_get_shared(dev, NULL);
|
||||
if (IS_ERR(rstc))
|
||||
return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
|
||||
/*
|
||||
* The reset also affects other HW that is not under the control
|
||||
* of Linux. Therefore, all we can do is deassert the reset.
|
||||
*/
|
||||
reset_control_deassert(rstc);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
|
||||
dev_name(dev), priv);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
|
||||
|
||||
adap = &priv->adap;
|
||||
adap->nr = pdev->id;
|
||||
adap->algo = &rzv2m_i2c_algo;
|
||||
adap->quirks = &rzv2m_i2c_quirks;
|
||||
adap->dev.parent = dev;
|
||||
adap->owner = THIS_MODULE;
|
||||
device_set_node(&adap->dev, dev_fwnode(dev));
|
||||
i2c_set_adapdata(adap, priv);
|
||||
strscpy(adap->name, pdev->name, sizeof(adap->name));
|
||||
init_completion(&priv->msg_tia_done);
|
||||
|
||||
ret = rzv2m_i2c_clock_calculate(dev, priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
pm_runtime_get_sync(dev);
|
||||
rzv2m_i2c_init(priv);
|
||||
pm_runtime_put(dev);
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = i2c_add_numbered_adapter(adap);
|
||||
if (ret < 0)
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rzv2m_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
struct device *dev = priv->adap.dev.parent;
|
||||
|
||||
i2c_del_adapter(&priv->adap);
|
||||
bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2m_i2c_suspend(struct device *dev)
|
||||
{
|
||||
struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2m_i2c_resume(struct device *dev)
|
||||
{
|
||||
struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = rzv2m_i2c_clock_calculate(dev, priv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
rzv2m_i2c_init(priv);
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2m_i2c_ids[] = {
|
||||
{ .compatible = "renesas,rzv2m-i2c" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
|
||||
|
||||
static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
|
||||
SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver rzv2m_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "rzv2m-i2c",
|
||||
.of_match_table = rzv2m_i2c_ids,
|
||||
.pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
|
||||
},
|
||||
.probe = rzv2m_i2c_probe,
|
||||
.remove = rzv2m_i2c_remove,
|
||||
};
|
||||
module_platform_driver(rzv2m_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
|
||||
MODULE_AUTHOR("Renesas Electronics Corporation");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue