From e0bd878a959008f02a1280b1dd2c128324586af3 Mon Sep 17 00:00:00 2001 From: Manasi Navare Date: Mon, 22 Jan 2018 14:43:10 -0800 Subject: [PATCH] drm/dp: Add HBR3 support in existing DRM DP helpers Existing helpers add support upto HBR2. This patch adds support for HBR3 rate (8.1 Gbps) introduced as part of DP 1.4 specification. Cc: Rodrigo Vivi Cc: Jani Nikula Cc: dri-devel@lists.freedesktop.org Signed-off-by: Manasi Navare Reviewed-by: Harry Wentland Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1516660991-20697-1-git-send-email-manasi.d.navare@intel.com --- drivers/gpu/drm/drm_dp_helper.c | 4 ++++ drivers/gpu/drm/drm_dp_mst_topology.c | 3 +++ include/drm/drm_dp_helper.h | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index adf79be42c1e..ffe14ec3e7f2 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -146,6 +146,8 @@ u8 drm_dp_link_rate_to_bw_code(int link_rate) return DP_LINK_BW_2_7; case 540000: return DP_LINK_BW_5_4; + case 810000: + return DP_LINK_BW_8_1; } } EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); @@ -161,6 +163,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw) return 270000; case DP_LINK_BW_5_4: return 540000; + case DP_LINK_BW_8_1: + return 810000; } } EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 70dcfa58d3c2..36df7df5fe1a 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -2087,6 +2087,9 @@ static bool drm_dp_get_vc_payload_bw(int dp_link_bw, case DP_LINK_BW_5_4: *out = 10 * dp_link_count; break; + case DP_LINK_BW_8_1: + *out = 15 * dp_link_count; + break; } return true; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index da58a428c8d7..418bf513a46c 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -334,6 +334,7 @@ # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14 /* 1.2 */ +# define DP_LINK_BW_8_1 0x1e /* 1.4 */ #define DP_LANE_COUNT_SET 0x101 # define DP_LANE_COUNT_MASK 0x0f