lib/raid6: Add AVX512 optimized gen_syndrome functions
Optimize RAID6 gen_syndrom functions to take advantage of the 512-bit ZMM integer instructions introduced in AVX512. AVX512 optimized gen_syndrom functions, which is simply based on avx2.c written by Yuanhan Liu and sse2.c written by hpa. The patch was tested and benchmarked before submission on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jim Kukunas <james.t.kukunas@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Megha Dey <megha.dey@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Shaohua Li <shli@fb.com>
This commit is contained in:
Gayatri Kammela
Shaohua Li
parent
d6385db941
commit
e0a491c129
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@ -163,11 +163,12 @@ asinstr += $(call as-instr,pshufb %xmm0$(comma)%xmm0,-DCONFIG_AS_SSSE3=1)
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asinstr += $(call as-instr,crc32l %eax$(comma)%eax,-DCONFIG_AS_CRC32=1)
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avx_instr := $(call as-instr,vxorps %ymm0$(comma)%ymm1$(comma)%ymm2,-DCONFIG_AS_AVX=1)
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avx2_instr :=$(call as-instr,vpbroadcastb %xmm0$(comma)%ymm1,-DCONFIG_AS_AVX2=1)
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avx512_instr :=$(call as-instr,vpmovm2b %k1$(comma)%zmm5,-DCONFIG_AS_AVX512=1)
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sha1_ni_instr :=$(call as-instr,sha1msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA1_NI=1)
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sha256_ni_instr :=$(call as-instr,sha256msg1 %xmm0$(comma)%xmm1,-DCONFIG_AS_SHA256_NI=1)
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KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(sha1_ni_instr) $(sha256_ni_instr)
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KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(sha1_ni_instr) $(sha256_ni_instr)
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KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr)
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KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) $(avx512_instr) $(sha1_ni_instr) $(sha256_ni_instr)
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LDFLAGS := -m elf_$(UTS_MACHINE)
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@ -102,6 +102,9 @@ extern const struct raid6_calls raid6_altivec8;
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extern const struct raid6_calls raid6_avx2x1;
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extern const struct raid6_calls raid6_avx2x2;
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extern const struct raid6_calls raid6_avx2x4;
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extern const struct raid6_calls raid6_avx512x1;
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extern const struct raid6_calls raid6_avx512x2;
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extern const struct raid6_calls raid6_avx512x4;
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extern const struct raid6_calls raid6_tilegx8;
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struct raid6_recov_calls {
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@ -3,7 +3,7 @@ obj-$(CONFIG_RAID6_PQ) += raid6_pq.o
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raid6_pq-y += algos.o recov.o tables.o int1.o int2.o int4.o \
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int8.o int16.o int32.o
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raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o
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raid6_pq-$(CONFIG_X86) += recov_ssse3.o recov_avx2.o mmx.o sse1.o sse2.o avx2.o avx512.o
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raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o
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raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o
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raid6_pq-$(CONFIG_TILEGX) += tilegx8.o
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@ -49,6 +49,10 @@ const struct raid6_calls * const raid6_algos[] = {
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&raid6_avx2x1,
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&raid6_avx2x2,
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#endif
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#ifdef CONFIG_AS_AVX512
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&raid6_avx512x1,
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&raid6_avx512x2,
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#endif
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#endif
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#if defined(__x86_64__) && !defined(__arch_um__)
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&raid6_sse2x1,
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@ -59,6 +63,11 @@ const struct raid6_calls * const raid6_algos[] = {
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&raid6_avx2x2,
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&raid6_avx2x4,
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#endif
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#ifdef CONFIG_AS_AVX512
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&raid6_avx512x1,
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&raid6_avx512x2,
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&raid6_avx512x4,
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#endif
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#endif
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#ifdef CONFIG_ALTIVEC
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&raid6_altivec1,
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@ -0,0 +1,294 @@
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/* -*- linux-c -*- --------------------------------------------------------
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* Author: Gayatri Kammela <gayatri.kammela@intel.com>
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* Author: Megha Dey <megha.dey@linux.intel.com>
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*
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* Based on avx2.c: Copyright 2012 Yuanhan Liu All Rights Reserved
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* Based on sse2.c: Copyright 2002 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* -----------------------------------------------------------------------
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*/
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/*
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* AVX512 implementation of RAID-6 syndrome functions
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*
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*/
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#ifdef CONFIG_AS_AVX512
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#include <linux/raid/pq.h>
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#include "x86.h"
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static const struct raid6_avx512_constants {
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u64 x1d[8];
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} raid6_avx512_constants __aligned(512) = {
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{ 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
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0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
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0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
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0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,},
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};
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static int raid6_have_avx512(void)
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{
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return boot_cpu_has(X86_FEATURE_AVX2) &&
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boot_cpu_has(X86_FEATURE_AVX) &&
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boot_cpu_has(X86_FEATURE_AVX512F) &&
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boot_cpu_has(X86_FEATURE_AVX512BW) &&
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boot_cpu_has(X86_FEATURE_AVX512VL) &&
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boot_cpu_has(X86_FEATURE_AVX512DQ);
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}
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static void raid6_avx5121_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0\n\t"
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"vpxorq %%zmm1,%%zmm1,%%zmm1" /* Zero temp */
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:
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: "m" (raid6_avx512_constants.x1d[0]));
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for (d = 0; d < bytes; d += 64) {
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asm volatile("prefetchnta %0\n\t"
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"vmovdqa64 %0,%%zmm2\n\t" /* P[0] */
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"prefetchnta %1\n\t"
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"vmovdqa64 %%zmm2,%%zmm4\n\t" /* Q[0] */
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"vmovdqa64 %1,%%zmm6"
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:
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: "m" (dptr[z0][d]), "m" (dptr[z0-1][d]));
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for (z = z0-2; z >= 0; z--) {
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asm volatile("prefetchnta %0\n\t"
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"vpcmpgtb %%zmm4,%%zmm1,%%k1\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm6,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm6,%%zmm4,%%zmm4\n\t"
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"vmovdqa64 %0,%%zmm6"
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:
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: "m" (dptr[z][d]));
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}
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asm volatile("vpcmpgtb %%zmm4,%%zmm1,%%k1\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm6,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm6,%%zmm4,%%zmm4\n\t"
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"vmovntdq %%zmm2,%0\n\t"
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"vpxorq %%zmm2,%%zmm2,%%zmm2\n\t"
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"vmovntdq %%zmm4,%1\n\t"
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"vpxorq %%zmm4,%%zmm4,%%zmm4"
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:
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: "m" (p[d]), "m" (q[d]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx512x1 = {
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raid6_avx5121_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_have_avx512,
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"avx512x1",
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1 /* Has cache hints */
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};
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/*
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* Unrolled-by-2 AVX512 implementation
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*/
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static void raid6_avx5122_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0\n\t"
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"vpxorq %%zmm1,%%zmm1,%%zmm1" /* Zero temp */
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:
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: "m" (raid6_avx512_constants.x1d[0]));
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/* We uniformly assume a single prefetch covers at least 64 bytes */
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for (d = 0; d < bytes; d += 128) {
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asm volatile("prefetchnta %0\n\t"
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"prefetchnta %1\n\t"
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"vmovdqa64 %0,%%zmm2\n\t" /* P[0] */
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"vmovdqa64 %1,%%zmm3\n\t" /* P[1] */
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"vmovdqa64 %%zmm2,%%zmm4\n\t" /* Q[0] */
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"vmovdqa64 %%zmm3,%%zmm6" /* Q[1] */
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:
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: "m" (dptr[z0][d]), "m" (dptr[z0][d+64]));
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for (z = z0-1; z >= 0; z--) {
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asm volatile("prefetchnta %0\n\t"
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"prefetchnta %1\n\t"
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"vpcmpgtb %%zmm4,%%zmm1,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm1,%%k2\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vmovdqa64 %0,%%zmm5\n\t"
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"vmovdqa64 %1,%%zmm7\n\t"
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"vpxorq %%zmm5,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm7,%%zmm3,%%zmm3\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6"
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:
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: "m" (dptr[z][d]), "m" (dptr[z][d+64]));
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}
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asm volatile("vmovntdq %%zmm2,%0\n\t"
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"vmovntdq %%zmm3,%1\n\t"
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"vmovntdq %%zmm4,%2\n\t"
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"vmovntdq %%zmm6,%3"
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:
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: "m" (p[d]), "m" (p[d+64]), "m" (q[d]),
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"m" (q[d+64]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx512x2 = {
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raid6_avx5122_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_have_avx512,
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"avx512x2",
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1 /* Has cache hints */
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};
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#ifdef CONFIG_X86_64
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/*
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* Unrolled-by-4 AVX2 implementation
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*/
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static void raid6_avx5124_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0\n\t"
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"vpxorq %%zmm1,%%zmm1,%%zmm1\n\t" /* Zero temp */
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"vpxorq %%zmm2,%%zmm2,%%zmm2\n\t" /* P[0] */
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"vpxorq %%zmm3,%%zmm3,%%zmm3\n\t" /* P[1] */
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"vpxorq %%zmm4,%%zmm4,%%zmm4\n\t" /* Q[0] */
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"vpxorq %%zmm6,%%zmm6,%%zmm6\n\t" /* Q[1] */
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"vpxorq %%zmm10,%%zmm10,%%zmm10\n\t" /* P[2] */
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"vpxorq %%zmm11,%%zmm11,%%zmm11\n\t" /* P[3] */
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"vpxorq %%zmm12,%%zmm12,%%zmm12\n\t" /* Q[2] */
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"vpxorq %%zmm14,%%zmm14,%%zmm14" /* Q[3] */
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:
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: "m" (raid6_avx512_constants.x1d[0]));
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for (d = 0; d < bytes; d += 256) {
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for (z = z0; z >= 0; z--) {
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asm volatile("prefetchnta %0\n\t"
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"prefetchnta %1\n\t"
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"prefetchnta %2\n\t"
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"prefetchnta %3\n\t"
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"vpcmpgtb %%zmm4,%%zmm1,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm1,%%k2\n\t"
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"vpcmpgtb %%zmm12,%%zmm1,%%k3\n\t"
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"vpcmpgtb %%zmm14,%%zmm1,%%k4\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpmovm2b %%k3,%%zmm13\n\t"
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"vpmovm2b %%k4,%%zmm15\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpaddb %%zmm12,%%zmm12,%%zmm12\n\t"
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"vpaddb %%zmm14,%%zmm14,%%zmm14\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpandq %%zmm0,%%zmm13,%%zmm13\n\t"
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"vpandq %%zmm0,%%zmm15,%%zmm15\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vpxorq %%zmm13,%%zmm12,%%zmm12\n\t"
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"vpxorq %%zmm15,%%zmm14,%%zmm14\n\t"
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"vmovdqa64 %0,%%zmm5\n\t"
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"vmovdqa64 %1,%%zmm7\n\t"
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"vmovdqa64 %2,%%zmm13\n\t"
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"vmovdqa64 %3,%%zmm15\n\t"
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"vpxorq %%zmm5,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm7,%%zmm3,%%zmm3\n\t"
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"vpxorq %%zmm13,%%zmm10,%%zmm10\n\t"
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"vpxorq %%zmm15,%%zmm11,%%zmm11\n"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vpxorq %%zmm13,%%zmm12,%%zmm12\n\t"
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"vpxorq %%zmm15,%%zmm14,%%zmm14"
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:
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: "m" (dptr[z][d]), "m" (dptr[z][d+64]),
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"m" (dptr[z][d+128]), "m" (dptr[z][d+192]));
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}
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asm volatile("vmovntdq %%zmm2,%0\n\t"
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"vpxorq %%zmm2,%%zmm2,%%zmm2\n\t"
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"vmovntdq %%zmm3,%1\n\t"
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"vpxorq %%zmm3,%%zmm3,%%zmm3\n\t"
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"vmovntdq %%zmm10,%2\n\t"
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"vpxorq %%zmm10,%%zmm10,%%zmm10\n\t"
|
||||
"vmovntdq %%zmm11,%3\n\t"
|
||||
"vpxorq %%zmm11,%%zmm11,%%zmm11\n\t"
|
||||
"vmovntdq %%zmm4,%4\n\t"
|
||||
"vpxorq %%zmm4,%%zmm4,%%zmm4\n\t"
|
||||
"vmovntdq %%zmm6,%5\n\t"
|
||||
"vpxorq %%zmm6,%%zmm6,%%zmm6\n\t"
|
||||
"vmovntdq %%zmm12,%6\n\t"
|
||||
"vpxorq %%zmm12,%%zmm12,%%zmm12\n\t"
|
||||
"vmovntdq %%zmm14,%7\n\t"
|
||||
"vpxorq %%zmm14,%%zmm14,%%zmm14"
|
||||
:
|
||||
: "m" (p[d]), "m" (p[d+64]), "m" (p[d+128]),
|
||||
"m" (p[d+192]), "m" (q[d]), "m" (q[d+64]),
|
||||
"m" (q[d+128]), "m" (q[d+192]));
|
||||
}
|
||||
|
||||
asm volatile("sfence" : : : "memory");
|
||||
kernel_fpu_end();
|
||||
}
|
||||
|
||||
const struct raid6_calls raid6_avx512x4 = {
|
||||
raid6_avx5124_gen_syndrome,
|
||||
NULL, /* XOR not yet implemented */
|
||||
raid6_have_avx512,
|
||||
"avx512x4",
|
||||
1 /* Has cache hints */
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_AS_AVX512 */
|
||||
|
|
@ -46,6 +46,16 @@ static inline void kernel_fpu_end(void)
|
|||
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
|
||||
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
|
||||
#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
|
||||
#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
|
||||
#define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 DQ (Double/Quad granular)
|
||||
* Instructions
|
||||
*/
|
||||
#define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 BW (Byte/Word granular)
|
||||
* Instructions
|
||||
*/
|
||||
#define X86_FEATURE_AVX512VL (9*32+31) /* AVX-512 VL (128/256 Vector Length)
|
||||
* Extensions
|
||||
*/
|
||||
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
|
||||
|
||||
/* Should work well enough on modern CPUs for testing */
|
||||
|
|
|
|||
Loading…
Reference in New Issue