iio: imx8qxp-adc: fix irq flood when call imx8qxp_adc_read_raw()
commit0fc3562a99
upstream. irq flood happen when run cat /sys/bus/iio/devices/iio:device0/in_voltage1_raw imx8qxp_adc_read_raw() { ... enable irq /* adc start */ writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG); ^^^^ trigger irq flood. wait_for_completion_interruptible_timeout(); readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO); ^^^^ clear irq here. ... } There is only FIFO watermark interrupt at this ADC controller. IRQ line will be assert until software read data from FIFO. So IRQ flood happen during wait_for_completion_interruptible_timeout(). Move FIFO read into irq handle to avoid irq flood. Fixes:1e23dcaa1a
("iio: imx8qxp-adc: Add driver support for NXP IMX8QXP ADC") Cc: stable@vger.kernel.org Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Cai Huoqing <cai.huoqing@linux.dev> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/r/20221201140110.2653501-1-Frank.Li@nxp.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -86,6 +86,8 @@
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#define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100)
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#define IMX8QXP_ADC_MAX_FIFO_SIZE 16
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struct imx8qxp_adc {
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struct device *dev;
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void __iomem *regs;
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@ -95,6 +97,7 @@ struct imx8qxp_adc {
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/* Serialise ADC channel reads */
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struct mutex lock;
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struct completion completion;
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u32 fifo[IMX8QXP_ADC_MAX_FIFO_SIZE];
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};
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#define IMX8QXP_ADC_CHAN(_idx) { \
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@ -238,8 +241,7 @@ static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev,
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return ret;
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}
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*val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
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readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
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*val = adc->fifo[0];
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mutex_unlock(&adc->lock);
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return IIO_VAL_INT;
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@ -265,10 +267,15 @@ static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
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{
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struct imx8qxp_adc *adc = dev_id;
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u32 fifo_count;
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int i;
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fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
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readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
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for (i = 0; i < fifo_count; i++)
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adc->fifo[i] = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK,
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readl_relaxed(adc->regs + IMX8QXP_ADR_ADC_RESFIFO));
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if (fifo_count)
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complete(&adc->completion);
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