[WATCHDOG] Add iTCO vendor specific support
Add vendor specific support to the intel TCO timer based watchdog devices. At this moment we only have additional support for some SuperMicro Inc. motherboards. Signed-off-by: Robert Seretny <lkpatches@paypc.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Wim Van Sebroeck
parent
58c6570add
commit
e033351d53
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@ -340,6 +340,14 @@ config ITCO_WDT
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To compile this driver as a module, choose M here: the
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module will be called iTCO_wdt.
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config ITCO_VENDOR_SUPPORT
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bool "Intel TCO Timer/Watchdog Specific Vendor Support"
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depends on ITCO_WDT
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---help---
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Add vendor specific support to the intel TCO timer based watchdog
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devices. At this moment we only have additional support for some
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SuperMicro Inc. motherboards.
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config SC1200_WDT
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tristate "National Semiconductor PC87307/PC97307 (ala SC1200) Watchdog"
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depends on WATCHDOG && X86
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@ -47,7 +47,7 @@ obj-$(CONFIG_IBMASR) += ibmasr.o
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obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
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obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o
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obj-$(CONFIG_I8XX_TCO) += i8xx_tco.o
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obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o
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obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o iTCO_vendor_support.o
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obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
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obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
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obj-$(CONFIG_PC87413_WDT) += pc87413_wdt.o
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@ -0,0 +1,307 @@
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/*
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* intel TCO vendor specific watchdog driver support
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*
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* (c) Copyright 2006 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
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* provide warranty for any of this software. This material is
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* provided "AS-IS" and at no charge.
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*/
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/*
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* Includes, defines, variables, module parameters, ...
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*/
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/* Module and version information */
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#define DRV_NAME "iTCO_vendor_support"
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#define DRV_VERSION "1.01"
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#define DRV_RELDATE "11-Nov-2006"
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#define PFX DRV_NAME ": "
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/* Includes */
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#include <linux/module.h> /* For module specific items */
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#include <linux/moduleparam.h> /* For new moduleparam's */
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#include <linux/types.h> /* For standard types (like size_t) */
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#include <linux/errno.h> /* For the -ENODEV/... values */
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#include <linux/kernel.h> /* For printk/panic/... */
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#include <linux/init.h> /* For __init/__exit/... */
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#include <linux/ioport.h> /* For io-port access */
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#include <asm/io.h> /* For inb/outb/... */
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/* iTCO defines */
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#define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */
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#define TCOBASE acpibase + 0x60 /* TCO base address */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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/* List of vendor support modes */
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#define SUPERMICRO_OLD_BOARD 1 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
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#define SUPERMICRO_NEW_BOARD 2 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
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static int vendorsupport = 0;
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module_param(vendorsupport, int, 0);
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MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+");
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/*
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* Vendor Specific Support
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*/
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/*
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* Vendor Support: 1
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* Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
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* iTCO chipset: ICH2
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*
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* Code contributed by: R. Seretny <lkpatches@paypc.com>
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* Documentation obtained by R. Seretny from SuperMicro Technical Support
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*
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* To enable Watchdog function:
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* BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
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* This setting enables SMI to clear the watchdog expired flag.
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* If BIOS or CPU fail which may cause SMI hang, then system will
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* reboot. When application starts to use watchdog function,
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* application has to take over the control from SMI.
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*
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* For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
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* function.
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*
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* Note: The system will reboot when Expire Flag is set TWICE.
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* So, if the watchdog timer is 20 seconds, then the maximum hang
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* time is about 40 seconds, and the minimum hang time is about
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* 20.6 seconds.
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*/
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static void supermicro_old_pre_start(unsigned long acpibase)
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{
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unsigned long val32;
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val32 = inl(SMI_EN);
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val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to activate watchdog */
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}
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static void supermicro_old_pre_stop(unsigned long acpibase)
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{
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unsigned long val32;
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val32 = inl(SMI_EN);
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val32 &= 0x00002000; /* Turn on SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to deactivate watchdog */
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}
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static void supermicro_old_pre_keepalive(unsigned long acpibase)
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{
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/* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
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/* Clear "Expire Flag" (Bit 3 of TC01_STS register) */
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outb(0x08, TCO1_STS);
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}
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/*
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* Vendor Support: 2
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* Board: Super Micro Computer Inc. P4SBx, P4DPx
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* iTCO chipset: ICH4
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*
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* Code contributed by: R. Seretny <lkpatches@paypc.com>
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* Documentation obtained by R. Seretny from SuperMicro Technical Support
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*
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* To enable Watchdog function:
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* 1. BIOS
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* For P4SBx:
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* BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
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* For P4DPx:
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* BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
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* This setting enables or disables Watchdog function. When enabled, the
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* default watchdog timer is set to be 5 minutes (about 4’35”). It is
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* enough to load and run the OS. The application (service or driver) has
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* to take over the control once OS is running up and before watchdog
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* expires.
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*
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* 2. JUMPER
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* For P4SBx: JP39
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* For P4DPx: JP37
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* This jumper is used for safety. Closed is enabled. This jumper
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* prevents user enables watchdog in BIOS by accident.
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*
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* To enable Watch Dog function, both BIOS and JUMPER must be enabled.
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*
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* The documentation lists motherboards P4SBx and P4DPx series as of
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* 20-March-2002. However, this code works flawlessly with much newer
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* motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
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*
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* The original iTCO driver as written does not actually reset the
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* watchdog timer on these machines, as a result they reboot after five
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* minutes.
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*
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* NOTE: You may leave the Watchdog function disabled in the SuperMicro
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* BIOS to avoid a "boot-race"... This driver will enable watchdog
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* functionality even if it's disabled in the BIOS once the /dev/watchdog
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* file is opened.
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*/
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/* I/O Port's */
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#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
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#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
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/* Control Register's */
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#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
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#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
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#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
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#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
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#define SM_ENDWATCH 0xAA /* Watchdog lock control page */
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#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
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/* (Bit 3: 0 = seconds, 1 = minutes */
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#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
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#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
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/* Bit 6: timer is reset by kbd interrupt */
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/* Bit 7: timer is reset by mouse interrupt */
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static void supermicro_new_unlock_watchdog(void)
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{
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outb(SM_WATCHPAGE, SM_REGINDEX); /* Write 0x87 to port 0x2e twice */
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outb(SM_WATCHPAGE, SM_REGINDEX);
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outb(SM_CTLPAGESW, SM_REGINDEX); /* Switch to watchdog control page */
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outb(SM_CTLPAGE, SM_DATAIO);
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}
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static void supermicro_new_lock_watchdog(void)
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{
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outb(SM_ENDWATCH, SM_REGINDEX);
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}
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static void supermicro_new_pre_start(unsigned int heartbeat)
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{
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unsigned int val;
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supermicro_new_unlock_watchdog();
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/* Watchdog timer setting needs to be in seconds*/
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outb(SM_COUNTMODE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0xF7;
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outb(val, SM_DATAIO);
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/* Write heartbeat interval to WDOG */
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outb (SM_WATCHTIMER, SM_REGINDEX);
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outb((heartbeat & 255), SM_DATAIO);
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/* Make sure keyboard/mouse interrupts don't interfere */
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outb(SM_RESETCONTROL, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0x3f;
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outb(val, SM_DATAIO);
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/* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
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outb(SM_WATCHENABLE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val |= 0x01;
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outb(val, SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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static void supermicro_new_pre_stop(void)
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{
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unsigned int val;
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supermicro_new_unlock_watchdog();
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/* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
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outb(SM_WATCHENABLE, SM_REGINDEX);
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val = inb(SM_DATAIO);
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val &= 0xFE;
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outb(val, SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
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{
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supermicro_new_unlock_watchdog();
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/* reset watchdog timeout to heartveat value */
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outb(SM_WATCHTIMER, SM_REGINDEX);
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outb((heartbeat & 255), SM_DATAIO);
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supermicro_new_lock_watchdog();
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}
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/*
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* Generic Support Functions
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*/
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void iTCO_vendor_pre_start(unsigned long acpibase,
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unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_OLD_BOARD)
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supermicro_old_pre_start(acpibase);
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else if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_start(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_start);
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void iTCO_vendor_pre_stop(unsigned long acpibase)
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{
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if (vendorsupport == SUPERMICRO_OLD_BOARD)
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supermicro_old_pre_stop(acpibase);
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else if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_stop();
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_stop);
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void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_OLD_BOARD)
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supermicro_old_pre_keepalive(acpibase);
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else if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_set_heartbeat(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
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void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_set_heartbeat(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
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int iTCO_vendor_check_noreboot_on(void)
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{
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switch(vendorsupport) {
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case SUPERMICRO_OLD_BOARD:
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return 0;
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default:
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return 1;
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}
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}
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EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
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static int __init iTCO_vendor_init_module(void)
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{
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printk (KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
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return 0;
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}
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static void __exit iTCO_vendor_exit_module(void)
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{
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printk (KERN_INFO PFX "Module Unloaded\n");
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}
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module_init(iTCO_vendor_init_module);
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module_exit(iTCO_vendor_exit_module);
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MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, R. Seretny <lkpatches@paypc.com>");
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MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
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MODULE_VERSION(DRV_VERSION);
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MODULE_LICENSE("GPL");
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@ -48,8 +48,8 @@
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/* Module and version information */
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#define DRV_NAME "iTCO_wdt"
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#define DRV_VERSION "1.00"
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#define DRV_RELDATE "08-Oct-2006"
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#define DRV_VERSION "1.01"
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#define DRV_RELDATE "11-Nov-2006"
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#define PFX DRV_NAME ": "
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/* Includes */
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@ -189,6 +189,21 @@ static int nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, int, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
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/* iTCO Vendor Specific Support hooks */
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#ifdef CONFIG_ITCO_VENDOR_SUPPORT
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extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
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extern void iTCO_vendor_pre_stop(unsigned long);
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extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
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extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
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extern int iTCO_vendor_check_noreboot_on(void);
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#else
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#define iTCO_vendor_pre_start(acpibase, heartbeat) {}
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#define iTCO_vendor_pre_stop(acpibase) {}
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#define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
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#define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
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#define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
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#endif
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/*
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* Some TCO specific functions
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*/
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@ -249,6 +264,8 @@ static int iTCO_wdt_start(void)
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
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/* disable chipset's NO_REBOOT bit */
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if (iTCO_wdt_unset_NO_REBOOT_bit()) {
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printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
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@ -273,6 +290,8 @@ static int iTCO_wdt_stop(void)
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
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/* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
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val = inw(TCO1_CNT);
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val |= 0x0800;
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@ -293,6 +312,8 @@ static int iTCO_wdt_keepalive(void)
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{
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spin_lock(&iTCO_wdt_private.io_lock);
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iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
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/* Reload the timer by writing to the TCO Timer Counter register */
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if (iTCO_wdt_private.iTCO_version == 2) {
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outw(0x01, TCO_RLD);
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@ -319,6 +340,8 @@ static int iTCO_wdt_set_heartbeat(int t)
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((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
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return -EINVAL;
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iTCO_vendor_pre_set_heartbeat(tmrval);
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/* Write new heartbeat to watchdog */
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if (iTCO_wdt_private.iTCO_version == 2) {
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spin_lock(&iTCO_wdt_private.io_lock);
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@ -569,7 +592,7 @@ static int iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent,
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}
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/* Check chipset's NO_REBOOT bit */
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if (iTCO_wdt_unset_NO_REBOOT_bit()) {
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if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
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printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
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ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
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goto out;
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