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ARM: l2c: exynos: remove cache size override 

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-19 12:07:34 +00:00
parent 24cb65feab
commit dfbdd3d554
1 changed files with 1 additions and 4 deletions
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5
arch/arm/mach-exynos/exynos.c
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@ -32,9 +32,6 @@
#include "mfc.h"
#include "regs-pmu.h"
#define L2_AUX_VAL 0x3c470001
#define L2_AUX_MASK 0xc200ffff
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@ -323,7 +320,7 @@ static int __init exynos4_l2x0_cache_init(void)
{
int ret;
ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
ret = l2x0_of_init(0x3c400001, 0xc20fffff);
if (ret)
return ret;