stmmac: add CSR Clock range selection
This patch adds the CSR Clock range selection. Original patch from Johannes Stezenbach fixed the CSR in the stmmac_mdio. We agreed to provide this through the platform instead of. Also thanks to Johannes for having tested it on ARM. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Johannes Stezenbach <js@sig21.net> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -78,6 +78,7 @@ struct stmmac_priv {
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unsigned int flow_ctrl;
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unsigned int pause;
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struct mii_bus *mii;
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int mii_clk_csr;
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u32 msg_enable;
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spinlock_t lock;
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@ -1704,6 +1704,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
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plat_dat = pdev->dev.platform_data;
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priv->bus_id = plat_dat->bus_id;
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priv->pbl = plat_dat->pbl; /* TLI */
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priv->mii_clk_csr = plat_dat->clk_csr;
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priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
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priv->enh_desc = plat_dat->enh_desc;
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priv->ioaddr = addr;
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@ -53,7 +53,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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int data;
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u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
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((phyreg << 6) & (0x000007C0)));
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regValue |= MII_BUSY; /* in case of GMAC */
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regValue |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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writel(regValue, priv->ioaddr + mii_address);
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@ -85,7 +85,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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(((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
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| MII_WRITE;
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value |= MII_BUSY;
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value |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
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/* Wait until any existing MII operation is complete */
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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@ -32,6 +32,7 @@
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struct plat_stmmacenet_data {
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int bus_id;
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int pbl;
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int clk_csr;
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int has_gmac;
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int enh_desc;
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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