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ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support 

The inline assembly differences for v6 vs. v7 are purely
optimizations. On a v7 processor, an mrc with the pc sets the
condition codes to the 28-31 bits of the register being read. It
just so happens that the TX/RX full bits the DCC support code is
testing for are high enough in the register to be put into the
condition codes. On a v6 processor, this "feature" isn't
implemented and thus we have to do the usual read, mask, test
operations to check for TX/RX full. Thus, we can drop the v7
implementation and just use the v6 implementation for both.

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Stephen Boyd 2011-03-23 22:46:15 +01:00 committed by Russell King
parent 8e8806990c
commit dfad549d98
3 changed files with 3 additions and 38 deletions
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10
arch/arm/boot/compressed/head.S
View File

@ -21,20 +21,12 @@
#if defined(CONFIG_DEBUG_ICEDCC) #if defined(CONFIG_DEBUG_ICEDCC)
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp .macro loadsp, rb, tmp
.endm .endm
.macro writeb, ch, rb .macro writeb, ch, rb
mcr p14, 0, \ch, c0, c5, 0 mcr p14, 0, \ch, c0, c5, 0
.endm .endm
#elif defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp
.endm
.macro writeb, ch, rb
wait: mrc p14, 0, pc, c0, c1, 0
bcs wait
mcr p14, 0, \ch, c0, c5, 0
.endm
#elif defined(CONFIG_CPU_XSCALE) #elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp .macro loadsp, rb, tmp
.endm .endm

12
arch/arm/boot/compressed/misc.c
View File

@ -36,7 +36,7 @@ extern void error(char *x);
#ifdef CONFIG_DEBUG_ICEDCC #ifdef CONFIG_DEBUG_ICEDCC
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
static void icedcc_putc(int ch) static void icedcc_putc(int ch)
{ {
@ -52,16 +52,6 @@ static void icedcc_putc(int ch)
asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
} }
#elif defined(CONFIG_CPU_V7)
static void icedcc_putc(int ch)
{
asm(
"wait: mrc p14, 0, pc, c0, c1, 0 \n\
bcs wait \n\
mcr p14, 0, %0, c0, c5, 0 "
: : "r" (ch));
}
#elif defined(CONFIG_CPU_XSCALE) #elif defined(CONFIG_CPU_XSCALE)

19
arch/arm/kernel/debug.S
View File

@ -25,7 +25,7 @@
.macro addruart, rp, rv .macro addruart, rp, rv
.endm .endm
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro senduart, rd, rx .macro senduart, rd, rx
mcr p14, 0, \rd, c0, c5, 0 mcr p14, 0, \rd, c0, c5, 0
@ -49,23 +49,6 @@
1002: 1002:
.endm .endm
#elif defined(CONFIG_CPU_V7)
.macro senduart, rd, rx
mcr p14, 0, \rd, c0, c5, 0
.endm
.macro busyuart, rd, rx
busy: mrc p14, 0, pc, c0, c1, 0
bcs busy
.endm
.macro waituart, rd, rx
wait: mrc p14, 0, pc, c0, c1, 0
bcs wait
.endm
#elif defined(CONFIG_CPU_XSCALE) #elif defined(CONFIG_CPU_XSCALE)
.macro senduart, rd, rx .macro senduart, rd, rx