clk: qcom: add parent map for regmap mux

Currently the driver assumes the register configuration value
is identical to its index in the parent map. This patch adds
the parent map field in regmap mux clock node which contains
the mapping of parent index with actual register configuration
value. If regmap node contains this parent map then the
configuration value will be taken from this
parent map instead of simply writing the index value.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Abhishek Sahu 2017-12-13 19:55:33 +05:30 committed by Stephen Boyd
parent f933d383df
commit df96401649
4 changed files with 18 additions and 11 deletions

View File

@ -25,16 +25,6 @@ struct freq_tbl {
u16 n; u16 n;
}; };
/**
* struct parent_map - map table for PLL source select configuration values
* @src: source PLL
* @cfg: configuration value
*/
struct parent_map {
u8 src;
u8 cfg;
};
/** /**
* struct mn - M/N:D counter * struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter * @mnctr_en_bit: bit to enable mn counter

View File

@ -35,6 +35,9 @@ static u8 mux_get_parent(struct clk_hw *hw)
val >>= mux->shift; val >>= mux->shift;
val &= mask; val &= mask;
if (mux->parent_map)
return qcom_find_src_index(hw, mux->parent_map, val);
return val; return val;
} }
@ -45,6 +48,9 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val; unsigned int val;
if (mux->parent_map)
index = mux->parent_map[index].cfg;
val = index; val = index;
val <<= mux->shift; val <<= mux->shift;

View File

@ -16,11 +16,13 @@
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include "clk-regmap.h" #include "clk-regmap.h"
#include "common.h"
struct clk_regmap_mux { struct clk_regmap_mux {
u32 reg; u32 reg;
u32 shift; u32 shift;
u32 width; u32 width;
const struct parent_map *parent_map;
struct clk_regmap clkr; struct clk_regmap clkr;
}; };

View File

@ -20,7 +20,6 @@ struct qcom_reset_map;
struct regmap; struct regmap;
struct freq_tbl; struct freq_tbl;
struct clk_hw; struct clk_hw;
struct parent_map;
#define PLL_LOCK_COUNT_SHIFT 8 #define PLL_LOCK_COUNT_SHIFT 8
#define PLL_LOCK_COUNT_MASK 0x3f #define PLL_LOCK_COUNT_MASK 0x3f
@ -39,6 +38,16 @@ struct qcom_cc_desc {
size_t num_gdscs; size_t num_gdscs;
}; };
/**
* struct parent_map - map table for source select configuration values
* @src: source
* @cfg: configuration value
*/
struct parent_map {
u8 src;
u8 cfg;
};
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate); unsigned long rate);
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,