clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain which generates the clocks for Cortex-A53 Quad-core processsor. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> [s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
parent
2a2f33e83d
commit
df40a13ca5
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@ -32,6 +32,8 @@ Required Properties:
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which generates clocks for 3D Graphics Engine IP.
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- "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
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which generates clocks for GSCALER IPs.
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- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
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which generates clocks for Cortex-A53 Quad-core processor.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -105,6 +107,10 @@ Required Properties:
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- aclk_gscl_111
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- aclk_gscl_333
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Input clocks for apollo clock controller:
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- oscclk
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- sclk_bus_pll_apollo
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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@ -289,6 +295,15 @@ Example 2: Examples of clock controller nodes are listed below.
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<&cmu_top CLK_ACLK_GSCL_333>;
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};
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cmu_apollo: clock-controller@11900000 {
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compatible = "samsung,exynos5433-cmu-apollo";
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reg = <0x11900000 0x1088>;
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#clock-cells = <1>;
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clock-names = "oscclk", "sclk_bus_pll_apollo";
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clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -3393,3 +3393,196 @@ static void __init exynos5433_cmu_gscl_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
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exynos5433_cmu_gscl_init);
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/*
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* Register offset definitions for CMU_APOLLO
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*/
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#define APOLLO_PLL_LOCK 0x0000
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#define APOLLO_PLL_CON0 0x0100
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#define APOLLO_PLL_CON1 0x0104
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#define APOLLO_PLL_FREQ_DET 0x010c
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#define MUX_SEL_APOLLO0 0x0200
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#define MUX_SEL_APOLLO1 0x0204
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#define MUX_SEL_APOLLO2 0x0208
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#define MUX_ENABLE_APOLLO0 0x0300
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#define MUX_ENABLE_APOLLO1 0x0304
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#define MUX_ENABLE_APOLLO2 0x0308
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#define MUX_STAT_APOLLO0 0x0400
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#define MUX_STAT_APOLLO1 0x0404
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#define MUX_STAT_APOLLO2 0x0408
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#define DIV_APOLLO0 0x0600
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#define DIV_APOLLO1 0x0604
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#define DIV_APOLLO_PLL_FREQ_DET 0x0608
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#define DIV_STAT_APOLLO0 0x0700
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#define DIV_STAT_APOLLO1 0x0704
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#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
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#define ENABLE_ACLK_APOLLO 0x0800
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#define ENABLE_PCLK_APOLLO 0x0900
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#define ENABLE_SCLK_APOLLO 0x0a00
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#define ENABLE_IP_APOLLO0 0x0b00
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#define ENABLE_IP_APOLLO1 0x0b04
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#define CLKOUT_CMU_APOLLO 0x0c00
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#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
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#define ARMCLK_STOPCTRL 0x1000
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#define APOLLO_PWR_CTRL 0x1020
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#define APOLLO_PWR_CTRL2 0x1024
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#define APOLLO_INTR_SPREAD_ENABLE 0x1080
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#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
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#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
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static unsigned long apollo_clk_regs[] __initdata = {
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APOLLO_PLL_LOCK,
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APOLLO_PLL_CON0,
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APOLLO_PLL_CON1,
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APOLLO_PLL_FREQ_DET,
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MUX_SEL_APOLLO0,
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MUX_SEL_APOLLO1,
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MUX_SEL_APOLLO2,
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MUX_ENABLE_APOLLO0,
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MUX_ENABLE_APOLLO1,
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MUX_ENABLE_APOLLO2,
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MUX_STAT_APOLLO0,
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MUX_STAT_APOLLO1,
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MUX_STAT_APOLLO2,
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DIV_APOLLO0,
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DIV_APOLLO1,
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DIV_APOLLO_PLL_FREQ_DET,
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DIV_STAT_APOLLO0,
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DIV_STAT_APOLLO1,
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DIV_STAT_APOLLO_PLL_FREQ_DET,
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ENABLE_ACLK_APOLLO,
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ENABLE_PCLK_APOLLO,
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ENABLE_SCLK_APOLLO,
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ENABLE_IP_APOLLO0,
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ENABLE_IP_APOLLO1,
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CLKOUT_CMU_APOLLO,
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CLKOUT_CMU_APOLLO_DIV_STAT,
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ARMCLK_STOPCTRL,
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APOLLO_PWR_CTRL,
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APOLLO_PWR_CTRL2,
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APOLLO_INTR_SPREAD_ENABLE,
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APOLLO_INTR_SPREAD_USE_STANDBYWFI,
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APOLLO_INTR_SPREAD_BLOCKING_DURATION,
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};
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/* list of all parent clock list */
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PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
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PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
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PNAME(mout_apollo_p) = { "mout_apollo_pll",
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"mout_bus_pll_apollo_user", };
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static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
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APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
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};
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static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
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/* MUX_SEL_APOLLO0 */
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MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
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MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
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/* MUX_SEL_APOLLO1 */
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MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
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mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
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/* MUX_SEL_APOLLO2 */
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MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
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0, 1, 0, CLK_MUX_READ_ONLY),
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};
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static struct samsung_div_clock apollo_div_clks[] __initdata = {
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/* DIV_APOLLO0 */
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DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
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DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
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DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
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DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
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DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
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DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
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DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
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DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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/* DIV_APOLLO1 */
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DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
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DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
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DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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};
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static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
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/* ENABLE_ACLK_APOLLO */
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GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
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"div_atclk_apollo", ENABLE_ACLK_APOLLO,
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6, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
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"div_atclk_apollo", ENABLE_ACLK_APOLLO,
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5, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
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"div_atclk_apollo", ENABLE_ACLK_APOLLO,
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4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
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"div_atclk_apollo", ENABLE_ACLK_APOLLO,
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3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
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"div_aclk_apollo", ENABLE_ACLK_APOLLO,
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2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
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"div_pclk_apollo", ENABLE_ACLK_APOLLO,
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1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
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"div_pclk_apollo", ENABLE_ACLK_APOLLO,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_APOLLO */
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GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
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"div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
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2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
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ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
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"div_pclk_apollo", ENABLE_PCLK_APOLLO,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_SCLK_APOLLO */
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GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
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ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
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ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
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ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info apollo_cmu_info __initdata = {
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.pll_clks = apollo_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
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.mux_clks = apollo_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
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.div_clks = apollo_div_clks,
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.nr_div_clks = ARRAY_SIZE(apollo_div_clks),
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.gate_clks = apollo_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
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.nr_clk_ids = APOLLO_NR_CLK,
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.clk_regs = apollo_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
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};
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static void __init exynos5433_cmu_apollo_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &apollo_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
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exynos5433_cmu_apollo_init);
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@ -854,4 +854,41 @@
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#define GSCL_NR_CLK 29
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/* CMU_APOLLO */
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#define CLK_FOUT_APOLLO_PLL 1
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#define CLK_MOUT_APOLLO_PLL 2
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#define CLK_MOUT_BUS_PLL_APOLLO_USER 3
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#define CLK_MOUT_APOLLO 4
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#define CLK_DIV_CNTCLK_APOLLO 5
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#define CLK_DIV_PCLK_DBG_APOLLO 6
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#define CLK_DIV_ATCLK_APOLLO 7
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#define CLK_DIV_PCLK_APOLLO 8
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#define CLK_DIV_ACLK_APOLLO 9
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#define CLK_DIV_APOLLO2 10
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#define CLK_DIV_APOLLO1 11
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#define CLK_DIV_SCLK_HPM_APOLLO 12
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#define CLK_DIV_APOLLO_PLL 13
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#define CLK_ACLK_ATBDS_APOLLO_3 14
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#define CLK_ACLK_ATBDS_APOLLO_2 15
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#define CLK_ACLK_ATBDS_APOLLO_1 16
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#define CLK_ACLK_ATBDS_APOLLO_0 17
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#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
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#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
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#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
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#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
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#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
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#define CLK_ACLK_AHB2APB_APOLLOP 23
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#define CLK_ACLK_APOLLONP_200 24
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#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
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#define CLK_PCLK_PMU_APOLLO 26
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#define CLK_PCLK_SYSREG_APOLLO 27
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#define CLK_CNTCLK_APOLLO 28
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#define CLK_SCLK_HPM_APOLLO 29
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#define CLK_SCLK_APOLLO 30
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#define APOLLO_NR_CLK 31
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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