parisc architecture fixes and updates for kernel v6.0-rc3:

* Fix emulation of fldw instruction on unaligned addresses
 * Fix "make ARCH=parisc64 randconfig" to return a 64-bit config
 * Prevent boot if trying to boot a 32-bit kernel compiled for PA8X00
   CPUs on 32-bit only machines
 * ccio-dma: Handle kmalloc failure in ccio_init_resources()
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Merge tag 'parisc-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc fixes from Helge Deller:
 "Some interesting background to the current patchset:

  It turned out that the fldw instruction (which loads a 32-bit word
  from memory into one half of a FP register) failed on unaligned
  addresses and even trashed some other random FP register instead. It's
  a trivial one-liner fix in the exception handler but this failure
  dates back to the very beginnings of the parisc-port. It's strange
  that it was never noticed before.

  Another patch fixes an annoyance noticed by Randy Dunlap. Running
  "make ARCH=parisc64 randconfig" always returned a 32-bit config,
  although one would expect a 64-bit config. Masahiro Yamada suggested
  to mimik sparc Kconfig code, which fixed the issue nicely. This
  allowed to drop some compiler build checks too.

  Third, it's possible to build an optimized 32-bit kernel for PA8X00
  (64-bit) CPUs, which then wouldn't start on 32-bit-only (PA1.x)
  machines. I've added a bootup check which prevents that and which
  prints a message to the console. This can be tested with qemu, which
  currently only supports 32-bit emulation.

  The other patches are usual clean-up stuff like added return value
  checks and typo fixes in comments.

  Summary:

   - Fix emulation of fldw instruction on unaligned addresses

   - Fix "make ARCH=parisc64 randconfig" to return a 64-bit config

   - Prevent boot if trying to boot a 32-bit kernel compiled for PA8X00
     CPUs on 32-bit only machines

   - ccio-dma: Handle kmalloc failure in ccio_init_resources()"

* tag 'parisc-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines
  parisc: ccio-dma: Handle kmalloc failure in ccio_init_resources()
  parisc: led: Move from strlcpy with unused retval to strscpy
  parisc: ccio-dma: Fix typo in comment
  Revert "parisc: Show error if wrong 32/64-bit compiler is being used"
  parisc: Make CONFIG_64BIT available for ARCH=parisc64 only
  parisc: Fix exception handler for fldw and fstw instructions
This commit is contained in:
Linus Torvalds 2022-08-23 13:42:31 -07:00
commit df0219d11b
6 changed files with 59 additions and 30 deletions

View File

@ -146,10 +146,10 @@ menu "Processor type and features"
choice
prompt "Processor type"
default PA7000
default PA7000 if "$(ARCH)" = "parisc"
config PA7000
bool "PA7000/PA7100"
bool "PA7000/PA7100" if "$(ARCH)" = "parisc"
help
This is the processor type of your CPU. This information is
used for optimizing purposes. In order to compile a kernel
@ -160,21 +160,21 @@ config PA7000
which is required on some machines.
config PA7100LC
bool "PA7100LC"
bool "PA7100LC" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-L processor, as used in the
712, 715/64, 715/80, 715/100, 715/100XC, 725/100, 743, 748,
D200, D210, D300, D310 and E-class
config PA7200
bool "PA7200"
bool "PA7200" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-T' processor, as used in the
C100, C110, J100, J110, J210XC, D250, D260, D350, D360,
K100, K200, K210, K220, K400, K410 and K420
config PA7300LC
bool "PA7300LC"
bool "PA7300LC" if "$(ARCH)" = "parisc"
help
Select this option for the PCX-L2 processor, as used in the
744, A180, B132L, B160L, B180L, C132L, C160L, C180L,
@ -224,17 +224,8 @@ config MLONGCALLS
Enabling this option will probably slow down your kernel.
config 64BIT
bool "64-bit kernel"
def_bool "$(ARCH)" = "parisc64"
depends on PA8X00
help
Enable this if you want to support 64bit kernel on PA-RISC platform.
At the moment, only people willing to use more than 2GB of RAM,
or having a 64bit-only capable PA-RISC machine should say Y here.
Since there is no 64bit userland on PA-RISC, there is no point to
enable this option otherwise. The 64bit kernel is significantly bigger
and slower than the 32bit one.
choice
prompt "Kernel page size"

View File

@ -12,14 +12,6 @@
#include <asm/barrier.h>
#include <linux/atomic.h>
/* compiler build environment sanity checks: */
#if !defined(CONFIG_64BIT) && defined(__LP64__)
#error "Please use 'ARCH=parisc' to build the 32-bit kernel."
#endif
#if defined(CONFIG_64BIT) && !defined(__LP64__)
#error "Please use 'ARCH=parisc64' to build the 64-bit kernel."
#endif
/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
* on use of volatile and __*_bit() (set/clear/change):
* *_bit() want use of volatile.

View File

@ -22,7 +22,7 @@
#include <linux/init.h>
#include <linux/pgtable.h>
.level PA_ASM_LEVEL
.level 1.1
__INITDATA
ENTRY(boot_args)
@ -70,6 +70,47 @@ $bss_loop:
stw,ma %arg2,4(%r1)
stw,ma %arg3,4(%r1)
#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20)
/* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU
* and halt kernel if we detect a PA1.x CPU. */
ldi 32,%r10
mtctl %r10,%cr11
.level 2.0
mfctl,w %cr11,%r10
.level 1.1
comib,<>,n 0,%r10,$cpu_ok
load32 PA(msg1),%arg0
ldi msg1_end-msg1,%arg1
$iodc_panic:
copy %arg0, %r10
copy %arg1, %r11
load32 PA(init_stack),%sp
#define MEM_CONS 0x3A0
ldw MEM_CONS+32(%r0),%arg0 // HPA
ldi ENTRY_IO_COUT,%arg1
ldw MEM_CONS+36(%r0),%arg2 // SPA
ldw MEM_CONS+8(%r0),%arg3 // layers
load32 PA(__bss_start),%r1
stw %r1,-52(%sp) // arg4
stw %r0,-56(%sp) // arg5
stw %r10,-60(%sp) // arg6 = ptr to text
stw %r11,-64(%sp) // arg7 = len
stw %r0,-68(%sp) // arg8
load32 PA(.iodc_panic_ret), %rp
ldw MEM_CONS+40(%r0),%r1 // ENTRY_IODC
bv,n (%r1)
.iodc_panic_ret:
b . /* wait endless with ... */
or %r10,%r10,%r10 /* qemu idle sleep */
msg1: .ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n"
msg1_end:
$cpu_ok:
#endif
.level PA_ASM_LEVEL
/* Initialize startup VM. Just map first 16/32 MB of memory */
load32 PA(swapper_pg_dir),%r4
mtctl %r4,%cr24 /* Initialize kernel root pointer */

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@ -93,7 +93,7 @@
#define R1(i) (((i)>>21)&0x1f)
#define R2(i) (((i)>>16)&0x1f)
#define R3(i) ((i)&0x1f)
#define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
#define IM5_2(i) IM((i)>>16,5)
#define IM5_3(i) IM((i),5)

View File

@ -268,7 +268,7 @@ static int ioc_count;
* Each bit can represent a number of pages.
* LSbs represent lower addresses (IOVA's).
*
* This was was copied from sba_iommu.c. Don't try to unify
* This was copied from sba_iommu.c. Don't try to unify
* the two resource managers unless a way to have different
* allocation policies is also adjusted. We'd like to avoid
* I/O TLB thrashing by having resource allocation policy
@ -1380,15 +1380,17 @@ ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
}
}
static void __init ccio_init_resources(struct ioc *ioc)
static int __init ccio_init_resources(struct ioc *ioc)
{
struct resource *res = ioc->mmio_region;
char *name = kmalloc(14, GFP_KERNEL);
if (unlikely(!name))
return -ENOMEM;
snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
return 0;
}
static int new_ioc_area(struct resource *res, unsigned long size,
@ -1543,7 +1545,10 @@ static int __init ccio_probe(struct parisc_device *dev)
return -ENOMEM;
}
ccio_ioc_init(ioc);
ccio_init_resources(ioc);
if (ccio_init_resources(ioc)) {
kfree(ioc);
return -ENOMEM;
}
hppa_dma_ops = &ccio_ops;
hba = kzalloc(sizeof(*hba), GFP_KERNEL);

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@ -646,7 +646,7 @@ int lcd_print( const char *str )
cancel_delayed_work_sync(&led_task);
/* copy display string to buffer for procfs */
strlcpy(lcd_text, str, sizeof(lcd_text));
strscpy(lcd_text, str, sizeof(lcd_text));
/* Set LCD Cursor to 1st character */
gsc_writeb(lcd_info.reset_cmd1, LCD_CMD_REG);