PCI: qcom: Use block IP version for operations
Presently, when support for a new SoC is added, the driver ops structures and functions are versioned with plain 1, 2, 3 etc. Instead use the block IP version number. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
This commit is contained in:
Varadarajan Narayanan
Bjorn Helgaas
parent
244e00071f
commit
deff11f884
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@ -61,7 +61,7 @@
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#define PERST_DELAY_US 1000
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struct qcom_pcie_resources_v0 {
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struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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@ -75,7 +75,7 @@ struct qcom_pcie_resources_v0 {
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struct regulator *vdda_refclk;
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};
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struct qcom_pcie_resources_v1 {
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struct qcom_pcie_resources_1_0_0 {
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struct clk *iface;
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struct clk *aux;
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struct clk *master_bus;
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@ -84,7 +84,7 @@ struct qcom_pcie_resources_v1 {
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struct regulator *vdda;
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};
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struct qcom_pcie_resources_v2 {
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struct qcom_pcie_resources_2_3_2 {
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struct clk *aux_clk;
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struct clk *master_clk;
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struct clk *slave_clk;
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@ -92,7 +92,7 @@ struct qcom_pcie_resources_v2 {
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struct clk *pipe_clk;
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};
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struct qcom_pcie_resources_v3 {
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struct qcom_pcie_resources_2_4_0 {
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struct clk *aux_clk;
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struct clk *master_clk;
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struct clk *slave_clk;
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@ -111,10 +111,10 @@ struct qcom_pcie_resources_v3 {
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};
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union qcom_pcie_resources {
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struct qcom_pcie_resources_v0 v0;
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struct qcom_pcie_resources_v1 v1;
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struct qcom_pcie_resources_v2 v2;
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struct qcom_pcie_resources_v3 v3;
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struct qcom_pcie_resources_1_0_0 v1_0_0;
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struct qcom_pcie_resources_2_1_0 v2_1_0;
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struct qcom_pcie_resources_2_3_2 v2_3_2;
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struct qcom_pcie_resources_2_4_0 v2_4_0;
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};
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struct qcom_pcie;
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@ -173,7 +173,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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return dw_pcie_wait_for_link(pci);
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}
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static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
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static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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@ -183,9 +183,9 @@ static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
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writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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}
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static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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@ -233,9 +233,9 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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return PTR_ERR_OR_ZERO(res->phy_reset);
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}
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static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
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static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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reset_control_assert(res->pci_reset);
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reset_control_assert(res->axi_reset);
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@ -250,9 +250,9 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
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regulator_disable(res->vdda_refclk);
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}
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static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
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static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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@ -368,9 +368,9 @@ err_refclk:
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return ret;
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}
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static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
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static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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@ -398,9 +398,9 @@ static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
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return PTR_ERR_OR_ZERO(res->core);
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}
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static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
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static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
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reset_control_assert(res->core);
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clk_disable_unprepare(res->slave_bus);
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@ -410,9 +410,9 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
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regulator_disable(res->vdda);
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}
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static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
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static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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int ret;
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@ -478,7 +478,7 @@ err_res:
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return ret;
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}
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static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
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static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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@ -488,9 +488,9 @@ static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
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writel(val, pcie->parf + PCIE20_PARF_LTSSM);
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}
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static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
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static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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@ -514,9 +514,9 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
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return PTR_ERR_OR_ZERO(res->pipe_clk);
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}
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static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
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static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
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clk_disable_unprepare(res->slave_clk);
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clk_disable_unprepare(res->master_clk);
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@ -524,16 +524,16 @@ static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
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clk_disable_unprepare(res->aux_clk);
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}
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static void qcom_pcie_post_deinit_v2(struct qcom_pcie *pcie)
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static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
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clk_disable_unprepare(res->pipe_clk);
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}
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static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
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static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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@ -596,9 +596,9 @@ err_cfg_clk:
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return ret;
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}
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static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
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static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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int ret;
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@ -612,9 +612,9 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
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return 0;
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}
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static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)
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static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
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struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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@ -685,9 +685,9 @@ static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)
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return 0;
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}
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static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)
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static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
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struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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reset_control_assert(res->axi_m_reset);
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reset_control_assert(res->axi_s_reset);
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@ -703,9 +703,9 @@ static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)
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clk_disable_unprepare(res->slave_clk);
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}
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static int qcom_pcie_init_v3(struct qcom_pcie *pcie)
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static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
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struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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@ -969,40 +969,44 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
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.rd_own_conf = qcom_pcie_rd_own_conf,
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};
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static const struct qcom_pcie_ops ops_v0 = {
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.get_resources = qcom_pcie_get_resources_v0,
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.init = qcom_pcie_init_v0,
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.deinit = qcom_pcie_deinit_v0,
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.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
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/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
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static const struct qcom_pcie_ops ops_2_1_0 = {
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.get_resources = qcom_pcie_get_resources_2_1_0,
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.init = qcom_pcie_init_2_1_0,
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.deinit = qcom_pcie_deinit_2_1_0,
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.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
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};
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static const struct qcom_pcie_ops ops_v1 = {
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.get_resources = qcom_pcie_get_resources_v1,
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.init = qcom_pcie_init_v1,
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.deinit = qcom_pcie_deinit_v1,
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.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
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/* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
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static const struct qcom_pcie_ops ops_1_0_0 = {
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.get_resources = qcom_pcie_get_resources_1_0_0,
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.init = qcom_pcie_init_1_0_0,
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.deinit = qcom_pcie_deinit_1_0_0,
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.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
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};
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static const struct qcom_pcie_ops ops_v2 = {
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.get_resources = qcom_pcie_get_resources_v2,
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.init = qcom_pcie_init_v2,
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.post_init = qcom_pcie_post_init_v2,
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.deinit = qcom_pcie_deinit_v2,
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.post_deinit = qcom_pcie_post_deinit_v2,
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.ltssm_enable = qcom_pcie_v2_ltssm_enable,
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/* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
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static const struct qcom_pcie_ops ops_2_3_2 = {
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.get_resources = qcom_pcie_get_resources_2_3_2,
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.init = qcom_pcie_init_2_3_2,
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.post_init = qcom_pcie_post_init_2_3_2,
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.deinit = qcom_pcie_deinit_2_3_2,
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.post_deinit = qcom_pcie_post_deinit_2_3_2,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
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static const struct qcom_pcie_ops ops_2_4_0 = {
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.get_resources = qcom_pcie_get_resources_2_4_0,
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.init = qcom_pcie_init_2_4_0,
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.deinit = qcom_pcie_deinit_2_4_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = qcom_pcie_link_up,
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};
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static const struct qcom_pcie_ops ops_v3 = {
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.get_resources = qcom_pcie_get_resources_v3,
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.init = qcom_pcie_init_v3,
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.deinit = qcom_pcie_deinit_v3,
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.ltssm_enable = qcom_pcie_v2_ltssm_enable,
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};
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static int qcom_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -1089,11 +1093,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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}
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static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
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{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
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{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
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{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
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{ .compatible = "qcom,pcie-ipq4019", .data = &ops_v3 },
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{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
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{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
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{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
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{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
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{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
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{ }
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};
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