ASoC: max98090: Different comp tables for different pclks
In addtion expand the table to handle other values of sysclk. Instead of making the table 3D, expand it to a more descriptive struct. The divisors are specified in Table 19 of the 98090 data sheet version 0p94. The dmic frequency was previously assumed. Instead make it explicit and configurable through device tree. This now handles independently set pclk and dmic frequency. Based on downstream work by Ralph Birt. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Dylan Reid
Mark Brown
parent
33ebcd9b45
commit
defcd98b16
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@ -16,6 +16,8 @@ Optional properties:
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- clock-names: Should be "mclk"
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- maxim,dmic-freq: Frequency at which to clock DMIC
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Pins on the device (for linking into audio routes):
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* MIC1
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@ -1826,27 +1826,155 @@ static int max98090_set_bias_level(struct snd_soc_codec *codec,
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return 0;
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}
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static const int comp_pclk_rates[] = {
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11289600, 12288000, 12000000, 13000000, 19200000
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};
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static const int dmic_micclk[] = {
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2, 2, 2, 2, 4, 2
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};
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static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
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static const int comp_lrclk_rates[] = {
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8000, 16000, 32000, 44100, 48000, 96000
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};
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static const int dmic_comp[6][6] = {
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{7, 8, 3, 3, 3, 3},
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{7, 8, 3, 3, 3, 3},
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{7, 8, 3, 3, 3, 3},
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{7, 8, 3, 1, 1, 1},
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{7, 8, 3, 1, 2, 2},
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{7, 8, 3, 3, 3, 3}
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struct dmic_table {
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int pclk;
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struct {
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int freq;
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int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
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} settings[6]; /* One for each dmic divisor. */
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};
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static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
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{
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.pclk = 11289600,
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.settings = {
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{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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},
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},
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{
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.pclk = 12000000,
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.settings = {
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{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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}
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},
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{
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.pclk = 12288000,
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.settings = {
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{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
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}
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},
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{
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.pclk = 13000000,
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.settings = {
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{ .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
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{ .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
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{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
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{ .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
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{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
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{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
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}
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},
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{
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.pclk = 19200000,
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.settings = {
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{ .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
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{ .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
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{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
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{ .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
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{ .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
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{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
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}
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},
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};
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static int max98090_find_divisor(int target_freq, int pclk)
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{
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int current_diff = INT_MAX;
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int test_diff = INT_MAX;
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int divisor_index = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
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test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
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if (test_diff < current_diff) {
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current_diff = test_diff;
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divisor_index = i;
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}
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}
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return divisor_index;
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}
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static int max98090_find_closest_pclk(int pclk)
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{
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int m1;
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int m2;
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int i;
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for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
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if (pclk == dmic_table[i].pclk)
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return i;
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if (pclk < dmic_table[i].pclk) {
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if (i == 0)
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return i;
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m1 = pclk - dmic_table[i-1].pclk;
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m2 = dmic_table[i].pclk - pclk;
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if (m1 < m2)
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return i - 1;
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else
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return i;
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}
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}
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return -EINVAL;
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}
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static int max98090_configure_dmic(struct max98090_priv *max98090,
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int target_dmic_clk, int pclk, int fs)
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{
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int micclk_index;
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int pclk_index;
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int dmic_freq;
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int dmic_comp;
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int i;
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pclk_index = max98090_find_closest_pclk(pclk);
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if (pclk_index < 0)
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return pclk_index;
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micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
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for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
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if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
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break;
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}
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dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
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dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
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regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
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M98090_MICCLK_MASK,
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micclk_index << M98090_MICCLK_SHIFT);
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regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
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M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
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dmic_comp << M98090_DMIC_COMP_SHIFT |
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dmic_freq << M98090_DMIC_FREQ_SHIFT);
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return 0;
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}
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static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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@ -1854,7 +1982,6 @@ static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_codec *codec = dai->codec;
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struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
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struct max98090_cdata *cdata;
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int i, j;
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cdata = &max98090->dai[0];
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max98090->bclk = snd_soc_params_to_bclk(params);
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@ -1893,27 +2020,8 @@ static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
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snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
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M98090_DHF_MASK, M98090_DHF_MASK);
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/* Check for supported PCLK to LRCLK ratios */
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for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
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if (comp_pclk_rates[j] == max98090->sysclk) {
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break;
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}
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}
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for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
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if (max98090->lrclk <= (comp_lrclk_rates[i] +
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comp_lrclk_rates[i + 1]) / 2) {
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break;
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}
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}
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snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
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M98090_MICCLK_MASK,
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dmic_micclk[j] << M98090_MICCLK_SHIFT);
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snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
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M98090_DMIC_COMP_MASK,
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dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
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max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
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max98090->lrclk);
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return 0;
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}
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@ -1944,12 +2052,15 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
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if ((freq >= 10000000) && (freq <= 20000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV1);
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max98090->pclk = freq;
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} else if ((freq > 20000000) && (freq <= 40000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV2);
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max98090->pclk = freq >> 1;
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} else if ((freq > 40000000) && (freq <= 60000000)) {
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snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
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M98090_PSCLK_DIV4);
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max98090->pclk = freq >> 2;
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} else {
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dev_err(codec->dev, "Invalid master clock frequency\n");
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return -EINVAL;
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@ -2324,6 +2435,7 @@ static int max98090_probe(struct snd_soc_codec *codec)
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/* Initialize private data */
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max98090->sysclk = (unsigned)-1;
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max98090->pclk = (unsigned)-1;
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max98090->master = false;
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cdata = &max98090->dai[0];
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@ -2463,6 +2575,11 @@ static int max98090_i2c_probe(struct i2c_client *i2c,
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i2c_set_clientdata(i2c, max98090);
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max98090->pdata = i2c->dev.platform_data;
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ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
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&max98090->dmic_freq);
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if (ret < 0)
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max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
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max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
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if (IS_ERR(max98090->regmap)) {
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ret = PTR_ERR(max98090->regmap);
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@ -11,6 +11,12 @@
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#ifndef _MAX98090_H
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#define _MAX98090_H
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/*
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* The default operating frequency for a DMIC attached to the codec.
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* This can be overridden by a device tree property.
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*/
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#define MAX98090_DEFAULT_DMIC_FREQ 2500000
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/*
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* MAX98090 Register Definitions
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*/
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@ -1518,8 +1524,10 @@ struct max98090_priv {
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struct max98090_pdata *pdata;
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struct clk *mclk;
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unsigned int sysclk;
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unsigned int pclk;
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unsigned int bclk;
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unsigned int lrclk;
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u32 dmic_freq;
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struct max98090_cdata dai[1];
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int jack_state;
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struct delayed_work jack_work;
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