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ARM: tegra: paz00: add support serial port on JP1 

UART-A is connected to JP1 and used by the bootloader for debugging
output while UART-D is connected to the mini-pcie expansion slot.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Marc Dietrich 2011-08-07 21:00:51 +02:00 committed by Olof Johansson
parent bc24ed4f21
commit de7164db70
1 changed files with 11 additions and 0 deletions
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11
arch/arm/mach-tegra/board-paz00.c
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@ -45,6 +45,16 @@
static struct plat_serial8250_port debug_uart_platform_data[] = { static struct plat_serial8250_port debug_uart_platform_data[] = {
{ {
/* serial port on JP1 */
.membase = IO_ADDRESS(TEGRA_UARTA_BASE),
.mapbase = TEGRA_UARTA_BASE,
.irq = INT_UARTA,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 216000000,
}, {
/* serial port on mini-pcie */
.membase = IO_ADDRESS(TEGRA_UARTD_BASE), .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
.mapbase = TEGRA_UARTD_BASE, .mapbase = TEGRA_UARTD_BASE,
.irq = INT_UARTD, .irq = INT_UARTD,
@ -94,6 +104,7 @@ static void __init tegra_paz00_fixup(struct machine_desc *desc,
static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
/* name parent rate enabled */ /* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "uartd", "pll_p", 216000000, true }, { "uartd", "pll_p", 216000000, true },
{ NULL, NULL, 0, 0}, { NULL, NULL, 0, 0},
}; };