Immutable branch between MFD and GPIO due for the v4.9 merge window
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This commit is contained in:
Linus Walleij
commit
de4b894182
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@ -4,7 +4,7 @@ STMPE is an MFD device which may expose the following inbuilt devices: gpio,
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keypad, touchscreen, adc, pwm, rotator.
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Required properties:
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- compatible : "st,stmpe[610|801|811|1601|2401|2403]"
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- compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
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- reg : I2C/SPI address of the device
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Optional properties:
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@ -20,6 +20,8 @@
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*/
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enum { REG_RE, REG_FE, REG_IE };
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enum { LSB, CSB, MSB };
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#define CACHE_NR_REGS 3
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/* No variant has more than 24 GPIOs */
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#define CACHE_NR_BANKS (24 / 8)
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@ -39,7 +41,7 @@ static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
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u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
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u8 mask = 1 << (offset % 8);
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int ret;
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@ -55,7 +57,7 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
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u8 reg = stmpe->regs[which] - (offset / 8);
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u8 reg = stmpe->regs[which + (offset / 8)];
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u8 mask = 1 << (offset % 8);
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/*
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@ -89,7 +91,7 @@ static int stmpe_gpio_direction_output(struct gpio_chip *chip,
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{
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
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u8 mask = 1 << (offset % 8);
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stmpe_gpio_set(chip, offset, val);
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@ -102,7 +104,7 @@ static int stmpe_gpio_direction_input(struct gpio_chip *chip,
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{
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
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u8 mask = 1 << (offset % 8);
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return stmpe_set_bits(stmpe, reg, mask, 0);
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@ -142,8 +144,9 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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/* STMPE801 doesn't have RE and FE registers */
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if (stmpe_gpio->stmpe->partnum == STMPE801)
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/* STMPE801 and STMPE 1600 don't have RE and FE registers */
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if (stmpe_gpio->stmpe->partnum == STMPE801 ||
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stmpe_gpio->stmpe->partnum == STMPE1600)
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return 0;
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if (type & IRQ_TYPE_EDGE_RISING)
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@ -173,17 +176,24 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
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static const u8 regmap[] = {
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[REG_RE] = STMPE_IDX_GPRER_LSB,
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[REG_FE] = STMPE_IDX_GPFER_LSB,
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[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
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static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
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[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
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[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
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[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
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[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
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[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
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[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
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[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
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[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
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[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
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};
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int i, j;
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for (i = 0; i < CACHE_NR_REGS; i++) {
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/* STMPE801 doesn't have RE and FE registers */
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if ((stmpe->partnum == STMPE801) &&
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(i != REG_IE))
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/* STMPE801 and STMPE1600 don't have RE and FE registers */
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if ((stmpe->partnum == STMPE801 ||
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stmpe->partnum == STMPE1600) &&
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(i != REG_IE))
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continue;
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for (j = 0; j < num_banks; j++) {
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@ -194,7 +204,7 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
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continue;
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stmpe_gpio->oldregs[i][j] = new;
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stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
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stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
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}
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}
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@ -216,11 +226,21 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = 1 << (offset % 8);
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stmpe_gpio->regs[REG_IE][regoffset] |= mask;
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/*
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* STMPE1600 workaround: to be able to get IRQ from pins,
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* a read must be done on GPMR register, or a write in
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* GPSR or GPCR registers
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*/
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if (stmpe->partnum == STMPE1600)
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stmpe_reg_read(stmpe,
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stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
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}
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static void stmpe_dbg_show_one(struct seq_file *s,
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@ -230,9 +250,9 @@ static void stmpe_dbg_show_one(struct seq_file *s,
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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const char *label = gpiochip_is_requested(gc, offset);
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
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bool val = !!stmpe_gpio_get(gc, offset);
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u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
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u8 bank = offset / 8;
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u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
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u8 mask = 1 << (offset % 8);
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int ret;
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u8 dir;
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@ -247,39 +267,72 @@ static void stmpe_dbg_show_one(struct seq_file *s,
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gpio, label ?: "(none)",
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val ? "hi" : "lo");
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} else {
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u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8);
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u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8);
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u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8);
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u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8);
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bool edge_det;
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bool rise;
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bool fall;
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u8 edge_det_reg;
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u8 rise_reg;
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u8 fall_reg;
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u8 irqen_reg;
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char *edge_det_values[] = {"edge-inactive",
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"edge-asserted",
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"not-supported"};
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char *rise_values[] = {"no-rising-edge-detection",
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"rising-edge-detection",
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"not-supported"};
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char *fall_values[] = {"no-falling-edge-detection",
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"falling-edge-detection",
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"not-supported"};
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#define NOT_SUPPORTED_IDX 2
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u8 edge_det = NOT_SUPPORTED_IDX;
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u8 rise = NOT_SUPPORTED_IDX;
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u8 fall = NOT_SUPPORTED_IDX;
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bool irqen;
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ret = stmpe_reg_read(stmpe, edge_det_reg);
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if (ret < 0)
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switch (stmpe->partnum) {
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case STMPE610:
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case STMPE811:
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case STMPE1601:
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case STMPE2401:
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case STMPE2403:
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edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
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ret = stmpe_reg_read(stmpe, edge_det_reg);
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if (ret < 0)
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return;
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edge_det = !!(ret & mask);
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case STMPE1801:
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rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
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fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
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ret = stmpe_reg_read(stmpe, rise_reg);
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if (ret < 0)
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return;
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rise = !!(ret & mask);
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ret = stmpe_reg_read(stmpe, fall_reg);
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if (ret < 0)
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return;
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fall = !!(ret & mask);
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case STMPE801:
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case STMPE1600:
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irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
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break;
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default:
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return;
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edge_det = !!(ret & mask);
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ret = stmpe_reg_read(stmpe, rise_reg);
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if (ret < 0)
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return;
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rise = !!(ret & mask);
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ret = stmpe_reg_read(stmpe, fall_reg);
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if (ret < 0)
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return;
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fall = !!(ret & mask);
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}
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ret = stmpe_reg_read(stmpe, irqen_reg);
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if (ret < 0)
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return;
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irqen = !!(ret & mask);
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seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s",
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seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
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gpio, label ?: "(none)",
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val ? "hi" : "lo",
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edge_det ? "edge-asserted" : "edge-inactive",
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irqen ? "IRQ-enabled" : "",
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rise ? " rising-edge-detection" : "",
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fall ? " falling-edge-detection" : "");
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edge_det_values[edge_det],
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irqen ? "IRQ-enabled" : "IRQ-disabled",
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rise_values[rise],
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fall_values[fall]);
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}
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}
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@ -307,18 +360,32 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
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{
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struct stmpe_gpio *stmpe_gpio = dev;
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struct stmpe *stmpe = stmpe_gpio->stmpe;
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u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
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u8 statmsbreg;
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
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u8 status[num_banks];
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int ret;
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int i;
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/*
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* the stmpe_block_read() call below, imposes to set statmsbreg
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* with the register located at the lowest address. As STMPE1600
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* variant is the only one which respect registers address's order
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* (LSB regs located at lowest address than MSB ones) whereas all
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* the others have a registers layout with MSB located before the
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* LSB regs.
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*/
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if (stmpe->partnum == STMPE1600)
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statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
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else
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statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
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ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
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if (ret < 0)
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return IRQ_NONE;
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for (i = 0; i < num_banks; i++) {
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int bank = num_banks - i - 1;
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int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
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num_banks - i - 1;
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unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
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unsigned int stat = status[i];
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@ -336,12 +403,18 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
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stat &= ~(1 << bit);
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}
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stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
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/* Edge detect register is not present on 801 */
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if (stmpe->partnum != STMPE801)
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stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
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+ i, status[i]);
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/*
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* interrupt status register write has no effect on
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* 801/1801/1600, bits are cleared when read.
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* Edge detect register is not present on 801/1600/1801
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*/
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if (stmpe->partnum != STMPE801 || stmpe->partnum != STMPE1600 ||
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stmpe->partnum != STMPE1801) {
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stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
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stmpe_reg_write(stmpe,
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stmpe->regs[STMPE_IDX_GPEDR_LSB + i],
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status[i]);
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}
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}
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return IRQ_HANDLED;
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@ -57,6 +57,7 @@ static const struct of_device_id stmpe_of_match[] = {
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{ .compatible = "st,stmpe610", .data = (void *)STMPE610, },
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{ .compatible = "st,stmpe801", .data = (void *)STMPE801, },
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{ .compatible = "st,stmpe811", .data = (void *)STMPE811, },
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{ .compatible = "st,stmpe1600", .data = (void *)STMPE1600, },
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{ .compatible = "st,stmpe1601", .data = (void *)STMPE1601, },
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{ .compatible = "st,stmpe1801", .data = (void *)STMPE1801, },
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{ .compatible = "st,stmpe2401", .data = (void *)STMPE2401, },
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@ -101,6 +102,7 @@ static const struct i2c_device_id stmpe_i2c_id[] = {
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{ "stmpe610", STMPE610 },
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{ "stmpe801", STMPE801 },
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{ "stmpe811", STMPE811 },
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{ "stmpe1600", STMPE1600 },
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{ "stmpe1601", STMPE1601 },
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{ "stmpe1801", STMPE1801 },
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{ "stmpe2401", STMPE2401 },
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@ -469,6 +469,8 @@ static const struct mfd_cell stmpe_ts_cell = {
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static const u8 stmpe811_regs[] = {
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[STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
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[STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
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[STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
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[STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
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[STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
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[STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
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@ -481,7 +483,7 @@ static const u8 stmpe811_regs[] = {
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[STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
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[STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
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[STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
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[STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED,
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[STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
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};
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static struct stmpe_variant_block stmpe811_blocks[] = {
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@ -511,7 +513,7 @@ static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
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if (blocks & STMPE_BLOCK_TOUCHSCREEN)
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mask |= STMPE811_SYS_CTRL2_TSC_OFF;
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||||
return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
|
||||
enable ? 0 : mask);
|
||||
}
|
||||
|
||||
|
|
@ -550,26 +552,90 @@ static struct stmpe_variant_info stmpe610 = {
|
|||
.get_altfunc = stmpe811_get_altfunc,
|
||||
};
|
||||
|
||||
/*
|
||||
* STMPE1600
|
||||
* Compared to all others STMPE variant, LSB and MSB regs are located in this
|
||||
* order : LSB addr
|
||||
* MSB addr + 1
|
||||
* As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
|
||||
*/
|
||||
|
||||
static const u8 stmpe1600_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL,
|
||||
[STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB,
|
||||
[STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB,
|
||||
[STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB,
|
||||
[STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB,
|
||||
[STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB,
|
||||
[STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB,
|
||||
[STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
|
||||
[STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
|
||||
[STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
|
||||
};
|
||||
|
||||
static struct stmpe_variant_block stmpe1600_blocks[] = {
|
||||
{
|
||||
.cell = &stmpe_gpio_cell,
|
||||
.irq = 0,
|
||||
.block = STMPE_BLOCK_GPIO,
|
||||
},
|
||||
};
|
||||
|
||||
static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
|
||||
bool enable)
|
||||
{
|
||||
if (blocks & STMPE_BLOCK_GPIO)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct stmpe_variant_info stmpe1600 = {
|
||||
.name = "stmpe1600",
|
||||
.id_val = STMPE1600_ID,
|
||||
.id_mask = 0xffff,
|
||||
.num_gpios = 16,
|
||||
.af_bits = 0,
|
||||
.regs = stmpe1600_regs,
|
||||
.blocks = stmpe1600_blocks,
|
||||
.num_blocks = ARRAY_SIZE(stmpe1600_blocks),
|
||||
.num_irqs = STMPE1600_NR_INTERNAL_IRQS,
|
||||
.enable = stmpe1600_enable,
|
||||
};
|
||||
|
||||
/*
|
||||
* STMPE1601
|
||||
*/
|
||||
|
||||
static const u8 stmpe1601_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
|
||||
[STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
|
||||
[STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
|
||||
[STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
|
||||
[STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
|
||||
[STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
|
||||
[STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
|
||||
[STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
|
||||
[STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
|
||||
[STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
|
||||
[STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
|
||||
[STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
|
||||
[STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
|
||||
[STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
|
||||
[STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
|
||||
[STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
|
||||
[STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
|
||||
[STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
|
||||
[STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
|
||||
[STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
|
||||
[STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
|
||||
[STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
|
||||
[STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
|
||||
[STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
|
||||
[STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB,
|
||||
};
|
||||
|
||||
static struct stmpe_variant_block stmpe1601_blocks[] = {
|
||||
|
|
@ -640,13 +706,13 @@ static int stmpe1601_autosleep(struct stmpe *stmpe,
|
|||
return timeout;
|
||||
}
|
||||
|
||||
ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
|
||||
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
|
||||
STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
|
||||
timeout);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
|
||||
STPME1601_AUTOSLEEP_ENABLE,
|
||||
STPME1601_AUTOSLEEP_ENABLE);
|
||||
}
|
||||
|
|
@ -671,7 +737,7 @@ static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
else
|
||||
mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
|
||||
enable ? mask : 0);
|
||||
}
|
||||
|
||||
|
|
@ -710,18 +776,33 @@ static struct stmpe_variant_info stmpe1601 = {
|
|||
*/
|
||||
static const u8 stmpe1801_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
|
||||
[STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
|
||||
[STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
|
||||
[STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
|
||||
[STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
|
||||
[STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
|
||||
[STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
|
||||
[STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
|
||||
[STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
|
||||
[STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
|
||||
[STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
|
||||
[STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
|
||||
[STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
|
||||
[STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
|
||||
[STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
|
||||
[STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
|
||||
[STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
|
||||
[STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
|
||||
[STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
|
||||
[STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
|
||||
[STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
|
||||
[STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
|
||||
[STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
|
||||
[STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW,
|
||||
[STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
|
||||
[STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
|
||||
[STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
|
||||
};
|
||||
|
||||
static struct stmpe_variant_block stmpe1801_blocks[] = {
|
||||
|
|
@ -751,22 +832,31 @@ static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
enable ? mask : 0);
|
||||
}
|
||||
|
||||
static int stmpe1801_reset(struct stmpe *stmpe)
|
||||
static int stmpe_reset(struct stmpe *stmpe)
|
||||
{
|
||||
u16 id_val = stmpe->variant->id_val;
|
||||
unsigned long timeout;
|
||||
int ret = 0;
|
||||
u8 reset_bit;
|
||||
|
||||
ret = __stmpe_set_bits(stmpe, STMPE1801_REG_SYS_CTRL,
|
||||
STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET);
|
||||
if (id_val == STMPE811_ID)
|
||||
/* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
|
||||
reset_bit = STMPE811_SYS_CTRL_RESET;
|
||||
else
|
||||
/* all other STMPE variant use bit 7 of SYS_CTRL register */
|
||||
reset_bit = STMPE_SYS_CTRL_RESET;
|
||||
|
||||
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
|
||||
reset_bit, reset_bit);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(100);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
ret = __stmpe_reg_read(stmpe, STMPE1801_REG_SYS_CTRL);
|
||||
ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET))
|
||||
if (!(ret & reset_bit))
|
||||
return 0;
|
||||
usleep_range(100, 200);
|
||||
}
|
||||
|
|
@ -794,20 +884,39 @@ static struct stmpe_variant_info stmpe1801 = {
|
|||
|
||||
static const u8 stmpe24xx_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
|
||||
[STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
|
||||
[STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
|
||||
[STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
|
||||
[STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
|
||||
[STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
|
||||
[STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
|
||||
[STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
|
||||
[STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
|
||||
[STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
|
||||
[STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
|
||||
[STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
|
||||
[STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
|
||||
[STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
|
||||
[STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
|
||||
[STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
|
||||
[STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
|
||||
[STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
|
||||
[STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
|
||||
[STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
|
||||
[STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
|
||||
[STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
|
||||
[STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
|
||||
[STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
|
||||
[STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
|
||||
[STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
|
||||
[STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
|
||||
[STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
|
||||
[STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
|
||||
[STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
|
||||
[STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
|
||||
[STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
|
||||
[STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
|
||||
};
|
||||
|
||||
|
|
@ -840,7 +949,7 @@ static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
if (blocks & STMPE_BLOCK_KEYPAD)
|
||||
mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
|
||||
enable ? mask : 0);
|
||||
}
|
||||
|
||||
|
|
@ -893,6 +1002,7 @@ static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
|
|||
[STMPE610] = &stmpe610,
|
||||
[STMPE801] = &stmpe801,
|
||||
[STMPE811] = &stmpe811,
|
||||
[STMPE1600] = &stmpe1600,
|
||||
[STMPE1601] = &stmpe1601,
|
||||
[STMPE1801] = &stmpe1801,
|
||||
[STMPE2401] = &stmpe2401,
|
||||
|
|
@ -919,7 +1029,8 @@ static irqreturn_t stmpe_irq(int irq, void *data)
|
|||
int ret;
|
||||
int i;
|
||||
|
||||
if (variant->id_val == STMPE801_ID) {
|
||||
if (variant->id_val == STMPE801_ID ||
|
||||
variant->id_val == STMPE1600_ID) {
|
||||
int base = irq_create_mapping(stmpe->domain, 0);
|
||||
|
||||
handle_nested_irq(base);
|
||||
|
|
@ -982,7 +1093,7 @@ static void stmpe_irq_sync_unlock(struct irq_data *data)
|
|||
continue;
|
||||
|
||||
stmpe->oldier[i] = new;
|
||||
stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new);
|
||||
stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
|
||||
}
|
||||
|
||||
mutex_unlock(&stmpe->irq_lock);
|
||||
|
|
@ -1088,20 +1199,18 @@ static int stmpe_chip_init(struct stmpe *stmpe)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (id == STMPE1801_ID) {
|
||||
ret = stmpe1801_reset(stmpe);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
ret = stmpe_reset(stmpe);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (stmpe->irq >= 0) {
|
||||
if (id == STMPE801_ID)
|
||||
icr = STMPE801_REG_SYS_CTRL_INT_EN;
|
||||
if (id == STMPE801_ID || id == STMPE1600_ID)
|
||||
icr = STMPE_SYS_CTRL_INT_EN;
|
||||
else
|
||||
icr = STMPE_ICR_LSB_GIM;
|
||||
|
||||
/* STMPE801 doesn't support Edge interrupts */
|
||||
if (id != STMPE801_ID) {
|
||||
/* STMPE801 and STMPE1600 don't support Edge interrupts */
|
||||
if (id != STMPE801_ID && id != STMPE1600_ID) {
|
||||
if (irq_trigger == IRQF_TRIGGER_FALLING ||
|
||||
irq_trigger == IRQF_TRIGGER_RISING)
|
||||
icr |= STMPE_ICR_LSB_EDGE;
|
||||
|
|
@ -1109,8 +1218,8 @@ static int stmpe_chip_init(struct stmpe *stmpe)
|
|||
|
||||
if (irq_trigger == IRQF_TRIGGER_RISING ||
|
||||
irq_trigger == IRQF_TRIGGER_HIGH) {
|
||||
if (id == STMPE801_ID)
|
||||
icr |= STMPE801_REG_SYS_CTRL_INT_HI;
|
||||
if (id == STMPE801_ID || id == STMPE1600_ID)
|
||||
icr |= STMPE_SYS_CTRL_INT_HI;
|
||||
else
|
||||
icr |= STMPE_ICR_LSB_HIGH;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -104,6 +104,10 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE_ICR_LSB_EDGE (1 << 1)
|
||||
#define STMPE_ICR_LSB_GIM (1 << 0)
|
||||
|
||||
#define STMPE_SYS_CTRL_RESET (1 << 7)
|
||||
#define STMPE_SYS_CTRL_INT_EN (1 << 2)
|
||||
#define STMPE_SYS_CTRL_INT_HI (1 << 0)
|
||||
|
||||
/*
|
||||
* STMPE801
|
||||
*/
|
||||
|
|
@ -119,13 +123,10 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE801_REG_GPIO_SET_PIN 0x11
|
||||
#define STMPE801_REG_GPIO_DIR 0x12
|
||||
|
||||
#define STMPE801_REG_SYS_CTRL_RESET (1 << 7)
|
||||
#define STMPE801_REG_SYS_CTRL_INT_EN (1 << 2)
|
||||
#define STMPE801_REG_SYS_CTRL_INT_HI (1 << 0)
|
||||
|
||||
/*
|
||||
* STMPE811
|
||||
*/
|
||||
#define STMPE811_ID 0x0811
|
||||
|
||||
#define STMPE811_IRQ_TOUCH_DET 0
|
||||
#define STMPE811_IRQ_FIFO_TH 1
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||||
|
|
@ -138,6 +139,7 @@ int stmpe_remove(struct stmpe *stmpe);
|
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#define STMPE811_NR_INTERNAL_IRQS 8
|
||||
|
||||
#define STMPE811_REG_CHIP_ID 0x00
|
||||
#define STMPE811_REG_SYS_CTRL 0x03
|
||||
#define STMPE811_REG_SYS_CTRL2 0x04
|
||||
#define STMPE811_REG_SPI_CFG 0x08
|
||||
#define STMPE811_REG_INT_CTRL 0x09
|
||||
|
|
@ -154,11 +156,34 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE811_REG_GPIO_FE 0x16
|
||||
#define STMPE811_REG_GPIO_AF 0x17
|
||||
|
||||
#define STMPE811_SYS_CTRL_RESET (1 << 1)
|
||||
|
||||
#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
|
||||
#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
|
||||
#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
|
||||
#define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
|
||||
|
||||
/*
|
||||
* STMPE1600
|
||||
*/
|
||||
#define STMPE1600_ID 0x0016
|
||||
#define STMPE1600_NR_INTERNAL_IRQS 16
|
||||
|
||||
#define STMPE1600_REG_CHIP_ID 0x00
|
||||
#define STMPE1600_REG_SYS_CTRL 0x03
|
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#define STMPE1600_REG_IEGPIOR_LSB 0x08
|
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#define STMPE1600_REG_IEGPIOR_MSB 0x09
|
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#define STMPE1600_REG_ISGPIOR_LSB 0x0A
|
||||
#define STMPE1600_REG_ISGPIOR_MSB 0x0B
|
||||
#define STMPE1600_REG_GPMR_LSB 0x10
|
||||
#define STMPE1600_REG_GPMR_MSB 0x11
|
||||
#define STMPE1600_REG_GPSR_LSB 0x12
|
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#define STMPE1600_REG_GPSR_MSB 0x13
|
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#define STMPE1600_REG_GPDR_LSB 0x14
|
||||
#define STMPE1600_REG_GPDR_MSB 0x15
|
||||
#define STMPE1600_REG_GPPIR_LSB 0x16
|
||||
#define STMPE1600_REG_GPPIR_MSB 0x17
|
||||
|
||||
/*
|
||||
* STMPE1601
|
||||
*/
|
||||
|
|
@ -175,19 +200,32 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
|
||||
#define STMPE1601_REG_SYS_CTRL 0x02
|
||||
#define STMPE1601_REG_SYS_CTRL2 0x03
|
||||
#define STMPE1601_REG_ICR_MSB 0x10
|
||||
#define STMPE1601_REG_ICR_LSB 0x11
|
||||
#define STMPE1601_REG_IER_MSB 0x12
|
||||
#define STMPE1601_REG_IER_LSB 0x13
|
||||
#define STMPE1601_REG_ISR_MSB 0x14
|
||||
#define STMPE1601_REG_CHIP_ID 0x80
|
||||
#define STMPE1601_REG_ISR_LSB 0x15
|
||||
#define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
|
||||
#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
|
||||
#define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
|
||||
#define STMPE1601_REG_GPIO_MP_LSB 0x87
|
||||
#define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
|
||||
#define STMPE1601_REG_CHIP_ID 0x80
|
||||
#define STMPE1601_REG_GPIO_SET_MSB 0x82
|
||||
#define STMPE1601_REG_GPIO_SET_LSB 0x83
|
||||
#define STMPE1601_REG_GPIO_CLR_MSB 0x84
|
||||
#define STMPE1601_REG_GPIO_CLR_LSB 0x85
|
||||
#define STMPE1601_REG_GPIO_MP_MSB 0x86
|
||||
#define STMPE1601_REG_GPIO_MP_LSB 0x87
|
||||
#define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
|
||||
#define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
|
||||
#define STMPE1601_REG_GPIO_ED_MSB 0x8A
|
||||
#define STMPE1601_REG_GPIO_ED_LSB 0x8B
|
||||
#define STMPE1601_REG_GPIO_RE_MSB 0x8C
|
||||
#define STMPE1601_REG_GPIO_RE_LSB 0x8D
|
||||
#define STMPE1601_REG_GPIO_FE_MSB 0x8E
|
||||
#define STMPE1601_REG_GPIO_FE_LSB 0x8F
|
||||
#define STMPE1601_REG_GPIO_PU_MSB 0x90
|
||||
#define STMPE1601_REG_GPIO_PU_LSB 0x91
|
||||
#define STMPE1601_REG_GPIO_AF_U_MSB 0x92
|
||||
|
||||
|
|
@ -243,8 +281,6 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
|
||||
#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
|
||||
|
||||
#define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7)
|
||||
|
||||
#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
|
||||
#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
|
||||
|
||||
|
|
@ -264,23 +300,48 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE24XX_NR_INTERNAL_IRQS 9
|
||||
|
||||
#define STMPE24XX_REG_SYS_CTRL 0x02
|
||||
#define STMPE24XX_REG_SYS_CTRL2 0x03
|
||||
#define STMPE24XX_REG_ICR_MSB 0x10
|
||||
#define STMPE24XX_REG_ICR_LSB 0x11
|
||||
#define STMPE24XX_REG_IER_MSB 0x12
|
||||
#define STMPE24XX_REG_IER_LSB 0x13
|
||||
#define STMPE24XX_REG_ISR_MSB 0x14
|
||||
#define STMPE24XX_REG_CHIP_ID 0x80
|
||||
#define STMPE24XX_REG_ISR_LSB 0x15
|
||||
#define STMPE24XX_REG_IEGPIOR_MSB 0x16
|
||||
#define STMPE24XX_REG_IEGPIOR_CSB 0x17
|
||||
#define STMPE24XX_REG_IEGPIOR_LSB 0x18
|
||||
#define STMPE24XX_REG_ISGPIOR_MSB 0x19
|
||||
#define STMPE24XX_REG_GPMR_LSB 0xA4
|
||||
#define STMPE24XX_REG_ISGPIOR_CSB 0x1A
|
||||
#define STMPE24XX_REG_ISGPIOR_LSB 0x1B
|
||||
#define STMPE24XX_REG_CHIP_ID 0x80
|
||||
#define STMPE24XX_REG_GPSR_MSB 0x83
|
||||
#define STMPE24XX_REG_GPSR_CSB 0x84
|
||||
#define STMPE24XX_REG_GPSR_LSB 0x85
|
||||
#define STMPE24XX_REG_GPCR_MSB 0x86
|
||||
#define STMPE24XX_REG_GPCR_CSB 0x87
|
||||
#define STMPE24XX_REG_GPCR_LSB 0x88
|
||||
#define STMPE24XX_REG_GPDR_MSB 0x89
|
||||
#define STMPE24XX_REG_GPDR_CSB 0x8A
|
||||
#define STMPE24XX_REG_GPDR_LSB 0x8B
|
||||
#define STMPE24XX_REG_GPEDR_MSB 0x8C
|
||||
#define STMPE24XX_REG_GPEDR_CSB 0x8D
|
||||
#define STMPE24XX_REG_GPEDR_LSB 0x8E
|
||||
#define STMPE24XX_REG_GPRER_MSB 0x8F
|
||||
#define STMPE24XX_REG_GPRER_CSB 0x90
|
||||
#define STMPE24XX_REG_GPRER_LSB 0x91
|
||||
#define STMPE24XX_REG_GPFER_MSB 0x92
|
||||
#define STMPE24XX_REG_GPFER_CSB 0x93
|
||||
#define STMPE24XX_REG_GPFER_LSB 0x94
|
||||
#define STMPE24XX_REG_GPPUR_MSB 0x95
|
||||
#define STMPE24XX_REG_GPPUR_CSB 0x96
|
||||
#define STMPE24XX_REG_GPPUR_LSB 0x97
|
||||
#define STMPE24XX_REG_GPPDR_LSB 0x9a
|
||||
#define STMPE24XX_REG_GPPDR_MSB 0x98
|
||||
#define STMPE24XX_REG_GPPDR_CSB 0x99
|
||||
#define STMPE24XX_REG_GPPDR_LSB 0x9A
|
||||
#define STMPE24XX_REG_GPAFR_U_MSB 0x9B
|
||||
|
||||
#define STMPE24XX_REG_GPMR_MSB 0xA2
|
||||
#define STMPE24XX_REG_GPMR_CSB 0xA3
|
||||
#define STMPE24XX_REG_GPMR_LSB 0xA4
|
||||
#define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
|
||||
#define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
|
||||
#define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ enum stmpe_partnum {
|
|||
STMPE610,
|
||||
STMPE801,
|
||||
STMPE811,
|
||||
STMPE1600,
|
||||
STMPE1601,
|
||||
STMPE1801,
|
||||
STMPE2401,
|
||||
|
|
@ -39,22 +40,42 @@ enum stmpe_partnum {
|
|||
*/
|
||||
enum {
|
||||
STMPE_IDX_CHIP_ID,
|
||||
STMPE_IDX_SYS_CTRL,
|
||||
STMPE_IDX_SYS_CTRL2,
|
||||
STMPE_IDX_ICR_LSB,
|
||||
STMPE_IDX_IER_LSB,
|
||||
STMPE_IDX_IER_MSB,
|
||||
STMPE_IDX_ISR_LSB,
|
||||
STMPE_IDX_ISR_MSB,
|
||||
STMPE_IDX_GPMR_LSB,
|
||||
STMPE_IDX_GPMR_CSB,
|
||||
STMPE_IDX_GPMR_MSB,
|
||||
STMPE_IDX_GPSR_LSB,
|
||||
STMPE_IDX_GPSR_CSB,
|
||||
STMPE_IDX_GPSR_MSB,
|
||||
STMPE_IDX_GPCR_LSB,
|
||||
STMPE_IDX_GPCR_CSB,
|
||||
STMPE_IDX_GPCR_MSB,
|
||||
STMPE_IDX_GPDR_LSB,
|
||||
STMPE_IDX_GPDR_CSB,
|
||||
STMPE_IDX_GPDR_MSB,
|
||||
STMPE_IDX_GPEDR_LSB,
|
||||
STMPE_IDX_GPEDR_CSB,
|
||||
STMPE_IDX_GPEDR_MSB,
|
||||
STMPE_IDX_GPRER_LSB,
|
||||
STMPE_IDX_GPRER_CSB,
|
||||
STMPE_IDX_GPRER_MSB,
|
||||
STMPE_IDX_GPFER_LSB,
|
||||
STMPE_IDX_GPFER_CSB,
|
||||
STMPE_IDX_GPFER_MSB,
|
||||
STMPE_IDX_GPPUR_LSB,
|
||||
STMPE_IDX_GPPDR_LSB,
|
||||
STMPE_IDX_GPAFR_U_MSB,
|
||||
STMPE_IDX_IEGPIOR_LSB,
|
||||
STMPE_IDX_IEGPIOR_CSB,
|
||||
STMPE_IDX_IEGPIOR_MSB,
|
||||
STMPE_IDX_ISGPIOR_LSB,
|
||||
STMPE_IDX_ISGPIOR_CSB,
|
||||
STMPE_IDX_ISGPIOR_MSB,
|
||||
STMPE_IDX_MAX,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue