ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after the cache has been enabled, and fixups have been run. We move the saving of the auxiliary control register into the ->save function as well which makes everything operate in a sane and maintainable way. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -202,6 +202,11 @@ static void l2x0_disable(void)
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raw_spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2c_save(void __iomem *base)
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{
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l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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}
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/*
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* L2C-210 specific code.
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*
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@ -295,6 +300,7 @@ static const struct l2c_init_data l2c210_data __initconst = {
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.way_size_0 = SZ_8K,
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.num_lock = 1,
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.enable = l2c_enable,
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.save = l2c_save,
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.outer_cache = {
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.inv_range = l2c210_inv_range,
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.clean_range = l2c210_clean_range,
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@ -439,6 +445,7 @@ static const struct l2c_init_data l2c220_data = {
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.way_size_0 = SZ_8K,
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.num_lock = 1,
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.enable = l2c_enable,
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.save = l2c_save,
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.outer_cache = {
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.inv_range = l2c220_inv_range,
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.clean_range = l2c220_clean_range,
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@ -575,6 +582,8 @@ static void __init l2c310_save(void __iomem *base)
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{
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unsigned revision;
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l2c_save(base);
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l2x0_saved_regs.tag_latency = readl_relaxed(base +
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L310_TAG_LATENCY_CTRL);
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l2x0_saved_regs.data_latency = readl_relaxed(base +
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@ -712,13 +721,6 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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unsigned way_size_bits, ways;
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u32 aux;
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/*
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* It is strange to save the register state before initialisation,
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* but hey, this is what the DT implementations decided to do.
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*/
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if (data->save)
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data->save(l2x0_base);
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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@ -777,14 +779,18 @@ static void __init __l2c_init(const struct l2c_init_data *data,
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
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data->enable(l2x0_base, aux, data->num_lock);
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outer_cache = fns;
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/*
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* It is strange to save the register state before initialisation,
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* but hey, this is what the DT implementations decided to do.
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*/
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if (data->save)
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data->save(l2x0_base);
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/* Re-read it in case some bits are reserved. */
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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/* Save the value for resuming. */
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l2x0_saved_regs.aux_ctrl = aux;
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outer_cache = fns;
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pr_info("%s cache controller enabled, %d ways, %d kB\n",
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data->type, ways, l2x0_size >> 10);
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pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
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@ -865,6 +871,7 @@ static const struct l2c_init_data of_l2c210_data __initconst = {
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.num_lock = 1,
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.of_parse = l2x0_of_parse,
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.enable = l2c_enable,
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.save = l2c_save,
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.outer_cache = {
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.inv_range = l2c210_inv_range,
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.clean_range = l2c210_clean_range,
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@ -882,6 +889,7 @@ static const struct l2c_init_data of_l2c220_data __initconst = {
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.num_lock = 1,
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.of_parse = l2x0_of_parse,
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.enable = l2c_enable,
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.save = l2c_save,
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.outer_cache = {
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.inv_range = l2c220_inv_range,
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.clean_range = l2c220_clean_range,
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@ -1296,6 +1304,8 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
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static void __init tauros3_save(void __iomem *base)
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{
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l2c_save(base);
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l2x0_saved_regs.aux2_ctrl =
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readl_relaxed(base + TAUROS3_AUX2_CTRL);
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l2x0_saved_regs.prefetch_ctrl =
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