edac: Move edac main structs to include/linux/edac.h
As we'll need to use those structs for trace functions, they should be on a more public place. So, move struct mem_ctl_info & friends to edac.h. No functional changes on this patch. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
224e871f36
commit
ddeb3547d4
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@ -34,11 +34,10 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/sysdev.h>
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#include <linux/workqueue.h>
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#include <linux/workqueue.h>
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#include <linux/edac.h>
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#define EDAC_MC_LABEL_LEN 31
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#define EDAC_DEVICE_NAME_LEN 31
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#define EDAC_DEVICE_NAME_LEN 31
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#define EDAC_ATTRIB_VALUE_LEN 15
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#define EDAC_ATTRIB_VALUE_LEN 15
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#define MC_PROC_NAME_MAX_LEN 7
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#if PAGE_SHIFT < 20
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#if PAGE_SHIFT < 20
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#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
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#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
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@ -101,353 +100,6 @@ extern int edac_debug_level;
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#define edac_dev_name(dev) (dev)->dev_name
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#define edac_dev_name(dev) (dev)->dev_name
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/* memory devices */
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enum dev_type {
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DEV_UNKNOWN = 0,
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DEV_X1,
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DEV_X2,
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DEV_X4,
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DEV_X8,
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DEV_X16,
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DEV_X32, /* Do these parts exist? */
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DEV_X64 /* Do these parts exist? */
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};
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#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
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#define DEV_FLAG_X1 BIT(DEV_X1)
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#define DEV_FLAG_X2 BIT(DEV_X2)
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#define DEV_FLAG_X4 BIT(DEV_X4)
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#define DEV_FLAG_X8 BIT(DEV_X8)
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#define DEV_FLAG_X16 BIT(DEV_X16)
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#define DEV_FLAG_X32 BIT(DEV_X32)
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#define DEV_FLAG_X64 BIT(DEV_X64)
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/* memory types */
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enum mem_type {
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MEM_EMPTY = 0, /* Empty csrow */
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MEM_RESERVED, /* Reserved csrow type */
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MEM_UNKNOWN, /* Unknown csrow type */
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MEM_FPM, /* Fast page mode */
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MEM_EDO, /* Extended data out */
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MEM_BEDO, /* Burst Extended data out */
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MEM_SDR, /* Single data rate SDRAM */
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MEM_RDR, /* Registered single data rate SDRAM */
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MEM_DDR, /* Double data rate SDRAM */
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MEM_RDDR, /* Registered Double data rate SDRAM */
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MEM_RMBS, /* Rambus DRAM */
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MEM_DDR2, /* DDR2 RAM */
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MEM_FB_DDR2, /* fully buffered DDR2 */
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MEM_RDDR2, /* Registered DDR2 RAM */
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MEM_XDR, /* Rambus XDR */
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MEM_DDR3, /* DDR3 RAM */
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MEM_RDDR3, /* Registered DDR3 RAM */
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
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#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
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#define MEM_FLAG_FPM BIT(MEM_FPM)
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#define MEM_FLAG_EDO BIT(MEM_EDO)
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#define MEM_FLAG_BEDO BIT(MEM_BEDO)
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#define MEM_FLAG_SDR BIT(MEM_SDR)
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#define MEM_FLAG_RDR BIT(MEM_RDR)
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#define MEM_FLAG_DDR BIT(MEM_DDR)
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#define MEM_FLAG_RDDR BIT(MEM_RDDR)
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#define MEM_FLAG_RMBS BIT(MEM_RMBS)
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#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
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#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
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#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
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#define MEM_FLAG_XDR BIT(MEM_XDR)
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#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
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#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
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/* chipset Error Detection and Correction capabilities and mode */
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enum edac_type {
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EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
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EDAC_NONE, /* Doesn't support ECC */
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EDAC_RESERVED, /* Reserved ECC type */
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EDAC_PARITY, /* Detects parity errors */
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EDAC_EC, /* Error Checking - no correction */
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EDAC_SECDED, /* Single bit error correction, Double detection */
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EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
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EDAC_S4ECD4ED, /* Chipkill x4 devices */
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EDAC_S8ECD8ED, /* Chipkill x8 devices */
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EDAC_S16ECD16ED, /* Chipkill x16 devices */
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};
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#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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#define EDAC_FLAG_NONE BIT(EDAC_NONE)
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#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
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#define EDAC_FLAG_EC BIT(EDAC_EC)
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#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
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#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
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#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
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#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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/* scrubbing capabilities */
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enum scrub_type {
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SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
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SCRUB_NONE, /* No scrubber */
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SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
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SCRUB_SW_SRC, /* Software scrub only errors */
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SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
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SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
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SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
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SCRUB_HW_SRC, /* Hardware scrub only errors */
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SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
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SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
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};
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#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
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#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
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#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
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#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
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#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
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#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
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#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
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/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
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/* EDAC internal operation states */
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#define OP_ALLOC 0x100
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#define OP_RUNNING_POLL 0x201
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#define OP_RUNNING_INTERRUPT 0x202
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#define OP_RUNNING_POLL_INTR 0x203
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#define OP_OFFLINE 0x300
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/*
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* There are several things to be aware of that aren't at all obvious:
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*
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*
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* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
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*
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* These are some of the many terms that are thrown about that don't always
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* mean what people think they mean (Inconceivable!). In the interest of
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* creating a common ground for discussion, terms and their definitions
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* will be established.
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*
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* Memory devices: The individual chip on a memory stick. These devices
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* commonly output 4 and 8 bits each. Grouping several
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* of these in parallel provides 64 bits which is common
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* for a memory stick.
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*
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* Memory Stick: A printed circuit board that aggregates multiple
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* memory devices in parallel. This is the atomic
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* memory component that is purchaseable by Joe consumer
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* and loaded into a memory socket.
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*
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* Socket: A physical connector on the motherboard that accepts
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* a single memory stick.
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*
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* Channel: Set of memory devices on a memory stick that must be
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* grouped in parallel with one or more additional
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* channels from other memory sticks. This parallel
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* grouping of the output from multiple channels are
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* necessary for the smallest granularity of memory access.
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* Some memory controllers are capable of single channel -
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* which means that memory sticks can be loaded
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* individually. Other memory controllers are only
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* capable of dual channel - which means that memory
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* sticks must be loaded as pairs (see "socket set").
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*
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* Chip-select row: All of the memory devices that are selected together.
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* for a single, minimum grain of memory access.
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* This selects all of the parallel memory devices across
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* all of the parallel channels. Common chip-select rows
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* for single channel are 64 bits, for dual channel 128
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* bits.
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*
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* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
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* Motherboards commonly drive two chip-select pins to
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* a memory stick. A single-ranked stick, will occupy
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* only one of those rows. The other will be unused.
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*
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* Double-Ranked stick: A double-ranked stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently.
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*
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* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
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* A double-sided stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently. "Double-sided"
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* is irrespective of the memory devices being mounted
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* on both sides of the memory stick.
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*
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* Socket set: All of the memory sticks that are required for
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* a single memory access or all of the memory sticks
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* spanned by a chip-select row. A single socket set
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* has two chip-select rows and if double-sided sticks
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* are used these will occupy those chip-select rows.
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*
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* Bank: This term is avoided because it is unclear when
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* needing to distinguish between chip-select rows and
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* socket sets.
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*
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* Controller pages:
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*
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* Physical pages:
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*
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* Virtual pages:
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*
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*
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* STRUCTURE ORGANIZATION AND CHOICES
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*
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*
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*
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* PS - I enjoyed writing all that about as much as you enjoyed reading it.
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*/
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struct channel_info {
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int chan_idx; /* channel index */
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u32 ce_count; /* Correctable Errors for this CHANNEL */
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char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
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struct csrow_info *csrow; /* the parent */
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};
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struct csrow_info {
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unsigned long first_page; /* first page number in dimm */
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unsigned long last_page; /* last page number in dimm */
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unsigned long page_mask; /* used for interleaving -
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* 0UL for non intlv
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*/
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u32 nr_pages; /* number of pages in csrow */
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u32 grain; /* granularity of reported error in bytes */
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int csrow_idx; /* the chip-select row */
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enum dev_type dtype; /* memory device type */
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u32 ue_count; /* Uncorrectable Errors for this csrow */
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u32 ce_count; /* Correctable Errors for this csrow */
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enum mem_type mtype; /* memory csrow type */
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enum edac_type edac_mode; /* EDAC mode for this csrow */
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struct mem_ctl_info *mci; /* the parent */
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struct kobject kobj; /* sysfs kobject for this csrow */
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/* channel information for this csrow */
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u32 nr_channels;
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struct channel_info *channels;
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};
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struct mcidev_sysfs_group {
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const char *name; /* group name */
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const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
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};
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struct mcidev_sysfs_group_kobj {
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struct list_head list; /* list for all instances within a mc */
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struct kobject kobj; /* kobj for the group */
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const struct mcidev_sysfs_group *grp; /* group description table */
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struct mem_ctl_info *mci; /* the parent */
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};
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/* mcidev_sysfs_attribute structure
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* used for driver sysfs attributes and in mem_ctl_info
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* sysfs top level entries
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*/
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struct mcidev_sysfs_attribute {
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/* It should use either attr or grp */
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struct attribute attr;
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const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
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/* Ops for show/store values at the attribute - not used on group */
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ssize_t (*show)(struct mem_ctl_info *,char *);
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ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
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};
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/* MEMORY controller information structure
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*/
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struct mem_ctl_info {
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struct list_head link; /* for global list of mem_ctl_info structs */
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struct module *owner; /* Module owner of this control struct */
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unsigned long mtype_cap; /* memory types supported by mc */
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unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
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unsigned long edac_cap; /* configuration capabilities - this is
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* closely related to edac_ctl_cap. The
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* difference is that the controller may be
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* capable of s4ecd4ed which would be listed
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* in edac_ctl_cap, but if channels aren't
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* capable of s4ecd4ed then the edac_cap would
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* not have that capability.
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*/
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unsigned long scrub_cap; /* chipset scrub capabilities */
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enum scrub_type scrub_mode; /* current scrub mode */
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/* Translates sdram memory scrub rate given in bytes/sec to the
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internal representation and configures whatever else needs
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to be configured.
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*/
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int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
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/* Get the current sdram memory scrub rate from the internal
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representation and converts it to the closest matching
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bandwidth in bytes/sec.
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*/
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int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
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/* pointer to edac checking routine */
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void (*edac_check) (struct mem_ctl_info * mci);
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/*
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* Remaps memory pages: controller pages to physical pages.
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* For most MC's, this will be NULL.
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*/
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/* FIXME - why not send the phys page to begin with? */
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unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
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unsigned long page);
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int mc_idx;
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int nr_csrows;
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struct csrow_info *csrows;
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/*
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* FIXME - what about controllers on other busses? - IDs must be
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* unique. dev pointer should be sufficiently unique, but
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* BUS:SLOT.FUNC numbers may not be unique.
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*/
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struct device *dev;
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const char *mod_name;
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const char *mod_ver;
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const char *ctl_name;
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const char *dev_name;
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char proc_name[MC_PROC_NAME_MAX_LEN + 1];
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void *pvt_info;
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u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
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u32 ce_noinfo_count; /* Correctable Errors w/o info */
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u32 ue_count; /* Total Uncorrectable Errors for this MC */
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u32 ce_count; /* Total Correctable Errors for this MC */
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unsigned long start_time; /* mci load start time (in jiffies) */
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struct completion complete;
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/* edac sysfs device control */
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struct kobject edac_mci_kobj;
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/* list for all grp instances within a mc */
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struct list_head grp_kobj_list;
|
|
||||||
|
|
||||||
/* Additional top controller level attributes, but specified
|
|
||||||
* by the low level driver.
|
|
||||||
*
|
|
||||||
* Set by the low level driver to provide attributes at the
|
|
||||||
* controller level, same level as 'ue_count' and 'ce_count' above.
|
|
||||||
* An array of structures, NULL terminated
|
|
||||||
*
|
|
||||||
* If attributes are desired, then set to array of attributes
|
|
||||||
* If no attributes are desired, leave NULL
|
|
||||||
*/
|
|
||||||
const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
|
|
||||||
|
|
||||||
/* work struct for this MC */
|
|
||||||
struct delayed_work work;
|
|
||||||
|
|
||||||
/* the internal state of this controller instance */
|
|
||||||
int op_state;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The following are the structures to provide for a generic
|
* The following are the structures to provide for a generic
|
||||||
* or abstract 'edac_device'. This set of structures and the
|
* or abstract 'edac_device'. This set of structures and the
|
||||||
|
|
|
||||||
|
|
@ -42,4 +42,354 @@ static inline void opstate_init(void)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define EDAC_MC_LABEL_LEN 31
|
||||||
|
#define MC_PROC_NAME_MAX_LEN 7
|
||||||
|
|
||||||
|
/* memory devices */
|
||||||
|
enum dev_type {
|
||||||
|
DEV_UNKNOWN = 0,
|
||||||
|
DEV_X1,
|
||||||
|
DEV_X2,
|
||||||
|
DEV_X4,
|
||||||
|
DEV_X8,
|
||||||
|
DEV_X16,
|
||||||
|
DEV_X32, /* Do these parts exist? */
|
||||||
|
DEV_X64 /* Do these parts exist? */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
|
||||||
|
#define DEV_FLAG_X1 BIT(DEV_X1)
|
||||||
|
#define DEV_FLAG_X2 BIT(DEV_X2)
|
||||||
|
#define DEV_FLAG_X4 BIT(DEV_X4)
|
||||||
|
#define DEV_FLAG_X8 BIT(DEV_X8)
|
||||||
|
#define DEV_FLAG_X16 BIT(DEV_X16)
|
||||||
|
#define DEV_FLAG_X32 BIT(DEV_X32)
|
||||||
|
#define DEV_FLAG_X64 BIT(DEV_X64)
|
||||||
|
|
||||||
|
/* memory types */
|
||||||
|
enum mem_type {
|
||||||
|
MEM_EMPTY = 0, /* Empty csrow */
|
||||||
|
MEM_RESERVED, /* Reserved csrow type */
|
||||||
|
MEM_UNKNOWN, /* Unknown csrow type */
|
||||||
|
MEM_FPM, /* Fast page mode */
|
||||||
|
MEM_EDO, /* Extended data out */
|
||||||
|
MEM_BEDO, /* Burst Extended data out */
|
||||||
|
MEM_SDR, /* Single data rate SDRAM */
|
||||||
|
MEM_RDR, /* Registered single data rate SDRAM */
|
||||||
|
MEM_DDR, /* Double data rate SDRAM */
|
||||||
|
MEM_RDDR, /* Registered Double data rate SDRAM */
|
||||||
|
MEM_RMBS, /* Rambus DRAM */
|
||||||
|
MEM_DDR2, /* DDR2 RAM */
|
||||||
|
MEM_FB_DDR2, /* fully buffered DDR2 */
|
||||||
|
MEM_RDDR2, /* Registered DDR2 RAM */
|
||||||
|
MEM_XDR, /* Rambus XDR */
|
||||||
|
MEM_DDR3, /* DDR3 RAM */
|
||||||
|
MEM_RDDR3, /* Registered DDR3 RAM */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
|
||||||
|
#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
|
||||||
|
#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
|
||||||
|
#define MEM_FLAG_FPM BIT(MEM_FPM)
|
||||||
|
#define MEM_FLAG_EDO BIT(MEM_EDO)
|
||||||
|
#define MEM_FLAG_BEDO BIT(MEM_BEDO)
|
||||||
|
#define MEM_FLAG_SDR BIT(MEM_SDR)
|
||||||
|
#define MEM_FLAG_RDR BIT(MEM_RDR)
|
||||||
|
#define MEM_FLAG_DDR BIT(MEM_DDR)
|
||||||
|
#define MEM_FLAG_RDDR BIT(MEM_RDDR)
|
||||||
|
#define MEM_FLAG_RMBS BIT(MEM_RMBS)
|
||||||
|
#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
|
||||||
|
#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
|
||||||
|
#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
|
||||||
|
#define MEM_FLAG_XDR BIT(MEM_XDR)
|
||||||
|
#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
|
||||||
|
#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
|
||||||
|
|
||||||
|
/* chipset Error Detection and Correction capabilities and mode */
|
||||||
|
enum edac_type {
|
||||||
|
EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
|
||||||
|
EDAC_NONE, /* Doesn't support ECC */
|
||||||
|
EDAC_RESERVED, /* Reserved ECC type */
|
||||||
|
EDAC_PARITY, /* Detects parity errors */
|
||||||
|
EDAC_EC, /* Error Checking - no correction */
|
||||||
|
EDAC_SECDED, /* Single bit error correction, Double detection */
|
||||||
|
EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
|
||||||
|
EDAC_S4ECD4ED, /* Chipkill x4 devices */
|
||||||
|
EDAC_S8ECD8ED, /* Chipkill x8 devices */
|
||||||
|
EDAC_S16ECD16ED, /* Chipkill x16 devices */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
|
||||||
|
#define EDAC_FLAG_NONE BIT(EDAC_NONE)
|
||||||
|
#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
|
||||||
|
#define EDAC_FLAG_EC BIT(EDAC_EC)
|
||||||
|
#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
|
||||||
|
#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
|
||||||
|
#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
|
||||||
|
#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
|
||||||
|
#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
|
||||||
|
|
||||||
|
/* scrubbing capabilities */
|
||||||
|
enum scrub_type {
|
||||||
|
SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
|
||||||
|
SCRUB_NONE, /* No scrubber */
|
||||||
|
SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
|
||||||
|
SCRUB_SW_SRC, /* Software scrub only errors */
|
||||||
|
SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
|
||||||
|
SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
|
||||||
|
SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
|
||||||
|
SCRUB_HW_SRC, /* Hardware scrub only errors */
|
||||||
|
SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
|
||||||
|
SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
|
||||||
|
#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
|
||||||
|
#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
|
||||||
|
#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
|
||||||
|
#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
|
||||||
|
#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
|
||||||
|
#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
|
||||||
|
#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
|
||||||
|
|
||||||
|
/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
|
||||||
|
|
||||||
|
/* EDAC internal operation states */
|
||||||
|
#define OP_ALLOC 0x100
|
||||||
|
#define OP_RUNNING_POLL 0x201
|
||||||
|
#define OP_RUNNING_INTERRUPT 0x202
|
||||||
|
#define OP_RUNNING_POLL_INTR 0x203
|
||||||
|
#define OP_OFFLINE 0x300
|
||||||
|
|
||||||
|
/*
|
||||||
|
* There are several things to be aware of that aren't at all obvious:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
|
||||||
|
*
|
||||||
|
* These are some of the many terms that are thrown about that don't always
|
||||||
|
* mean what people think they mean (Inconceivable!). In the interest of
|
||||||
|
* creating a common ground for discussion, terms and their definitions
|
||||||
|
* will be established.
|
||||||
|
*
|
||||||
|
* Memory devices: The individual chip on a memory stick. These devices
|
||||||
|
* commonly output 4 and 8 bits each. Grouping several
|
||||||
|
* of these in parallel provides 64 bits which is common
|
||||||
|
* for a memory stick.
|
||||||
|
*
|
||||||
|
* Memory Stick: A printed circuit board that aggregates multiple
|
||||||
|
* memory devices in parallel. This is the atomic
|
||||||
|
* memory component that is purchaseable by Joe consumer
|
||||||
|
* and loaded into a memory socket.
|
||||||
|
*
|
||||||
|
* Socket: A physical connector on the motherboard that accepts
|
||||||
|
* a single memory stick.
|
||||||
|
*
|
||||||
|
* Channel: Set of memory devices on a memory stick that must be
|
||||||
|
* grouped in parallel with one or more additional
|
||||||
|
* channels from other memory sticks. This parallel
|
||||||
|
* grouping of the output from multiple channels are
|
||||||
|
* necessary for the smallest granularity of memory access.
|
||||||
|
* Some memory controllers are capable of single channel -
|
||||||
|
* which means that memory sticks can be loaded
|
||||||
|
* individually. Other memory controllers are only
|
||||||
|
* capable of dual channel - which means that memory
|
||||||
|
* sticks must be loaded as pairs (see "socket set").
|
||||||
|
*
|
||||||
|
* Chip-select row: All of the memory devices that are selected together.
|
||||||
|
* for a single, minimum grain of memory access.
|
||||||
|
* This selects all of the parallel memory devices across
|
||||||
|
* all of the parallel channels. Common chip-select rows
|
||||||
|
* for single channel are 64 bits, for dual channel 128
|
||||||
|
* bits.
|
||||||
|
*
|
||||||
|
* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
|
||||||
|
* Motherboards commonly drive two chip-select pins to
|
||||||
|
* a memory stick. A single-ranked stick, will occupy
|
||||||
|
* only one of those rows. The other will be unused.
|
||||||
|
*
|
||||||
|
* Double-Ranked stick: A double-ranked stick has two chip-select rows which
|
||||||
|
* access different sets of memory devices. The two
|
||||||
|
* rows cannot be accessed concurrently.
|
||||||
|
*
|
||||||
|
* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
|
||||||
|
* A double-sided stick has two chip-select rows which
|
||||||
|
* access different sets of memory devices. The two
|
||||||
|
* rows cannot be accessed concurrently. "Double-sided"
|
||||||
|
* is irrespective of the memory devices being mounted
|
||||||
|
* on both sides of the memory stick.
|
||||||
|
*
|
||||||
|
* Socket set: All of the memory sticks that are required for
|
||||||
|
* a single memory access or all of the memory sticks
|
||||||
|
* spanned by a chip-select row. A single socket set
|
||||||
|
* has two chip-select rows and if double-sided sticks
|
||||||
|
* are used these will occupy those chip-select rows.
|
||||||
|
*
|
||||||
|
* Bank: This term is avoided because it is unclear when
|
||||||
|
* needing to distinguish between chip-select rows and
|
||||||
|
* socket sets.
|
||||||
|
*
|
||||||
|
* Controller pages:
|
||||||
|
*
|
||||||
|
* Physical pages:
|
||||||
|
*
|
||||||
|
* Virtual pages:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* STRUCTURE ORGANIZATION AND CHOICES
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* PS - I enjoyed writing all that about as much as you enjoyed reading it.
|
||||||
|
*/
|
||||||
|
|
||||||
|
struct channel_info {
|
||||||
|
int chan_idx; /* channel index */
|
||||||
|
u32 ce_count; /* Correctable Errors for this CHANNEL */
|
||||||
|
char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
|
||||||
|
struct csrow_info *csrow; /* the parent */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct csrow_info {
|
||||||
|
unsigned long first_page; /* first page number in dimm */
|
||||||
|
unsigned long last_page; /* last page number in dimm */
|
||||||
|
unsigned long page_mask; /* used for interleaving -
|
||||||
|
* 0UL for non intlv
|
||||||
|
*/
|
||||||
|
u32 nr_pages; /* number of pages in csrow */
|
||||||
|
u32 grain; /* granularity of reported error in bytes */
|
||||||
|
int csrow_idx; /* the chip-select row */
|
||||||
|
enum dev_type dtype; /* memory device type */
|
||||||
|
u32 ue_count; /* Uncorrectable Errors for this csrow */
|
||||||
|
u32 ce_count; /* Correctable Errors for this csrow */
|
||||||
|
enum mem_type mtype; /* memory csrow type */
|
||||||
|
enum edac_type edac_mode; /* EDAC mode for this csrow */
|
||||||
|
struct mem_ctl_info *mci; /* the parent */
|
||||||
|
|
||||||
|
struct kobject kobj; /* sysfs kobject for this csrow */
|
||||||
|
|
||||||
|
/* channel information for this csrow */
|
||||||
|
u32 nr_channels;
|
||||||
|
struct channel_info *channels;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mcidev_sysfs_group {
|
||||||
|
const char *name; /* group name */
|
||||||
|
const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mcidev_sysfs_group_kobj {
|
||||||
|
struct list_head list; /* list for all instances within a mc */
|
||||||
|
|
||||||
|
struct kobject kobj; /* kobj for the group */
|
||||||
|
|
||||||
|
const struct mcidev_sysfs_group *grp; /* group description table */
|
||||||
|
struct mem_ctl_info *mci; /* the parent */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* mcidev_sysfs_attribute structure
|
||||||
|
* used for driver sysfs attributes and in mem_ctl_info
|
||||||
|
* sysfs top level entries
|
||||||
|
*/
|
||||||
|
struct mcidev_sysfs_attribute {
|
||||||
|
/* It should use either attr or grp */
|
||||||
|
struct attribute attr;
|
||||||
|
const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
|
||||||
|
|
||||||
|
/* Ops for show/store values at the attribute - not used on group */
|
||||||
|
ssize_t (*show)(struct mem_ctl_info *,char *);
|
||||||
|
ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
|
||||||
|
};
|
||||||
|
|
||||||
|
/* MEMORY controller information structure
|
||||||
|
*/
|
||||||
|
struct mem_ctl_info {
|
||||||
|
struct list_head link; /* for global list of mem_ctl_info structs */
|
||||||
|
|
||||||
|
struct module *owner; /* Module owner of this control struct */
|
||||||
|
|
||||||
|
unsigned long mtype_cap; /* memory types supported by mc */
|
||||||
|
unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
|
||||||
|
unsigned long edac_cap; /* configuration capabilities - this is
|
||||||
|
* closely related to edac_ctl_cap. The
|
||||||
|
* difference is that the controller may be
|
||||||
|
* capable of s4ecd4ed which would be listed
|
||||||
|
* in edac_ctl_cap, but if channels aren't
|
||||||
|
* capable of s4ecd4ed then the edac_cap would
|
||||||
|
* not have that capability.
|
||||||
|
*/
|
||||||
|
unsigned long scrub_cap; /* chipset scrub capabilities */
|
||||||
|
enum scrub_type scrub_mode; /* current scrub mode */
|
||||||
|
|
||||||
|
/* Translates sdram memory scrub rate given in bytes/sec to the
|
||||||
|
internal representation and configures whatever else needs
|
||||||
|
to be configured.
|
||||||
|
*/
|
||||||
|
int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
|
||||||
|
|
||||||
|
/* Get the current sdram memory scrub rate from the internal
|
||||||
|
representation and converts it to the closest matching
|
||||||
|
bandwidth in bytes/sec.
|
||||||
|
*/
|
||||||
|
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
|
||||||
|
|
||||||
|
|
||||||
|
/* pointer to edac checking routine */
|
||||||
|
void (*edac_check) (struct mem_ctl_info * mci);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Remaps memory pages: controller pages to physical pages.
|
||||||
|
* For most MC's, this will be NULL.
|
||||||
|
*/
|
||||||
|
/* FIXME - why not send the phys page to begin with? */
|
||||||
|
unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
|
||||||
|
unsigned long page);
|
||||||
|
int mc_idx;
|
||||||
|
int nr_csrows;
|
||||||
|
struct csrow_info *csrows;
|
||||||
|
/*
|
||||||
|
* FIXME - what about controllers on other busses? - IDs must be
|
||||||
|
* unique. dev pointer should be sufficiently unique, but
|
||||||
|
* BUS:SLOT.FUNC numbers may not be unique.
|
||||||
|
*/
|
||||||
|
struct device *dev;
|
||||||
|
const char *mod_name;
|
||||||
|
const char *mod_ver;
|
||||||
|
const char *ctl_name;
|
||||||
|
const char *dev_name;
|
||||||
|
char proc_name[MC_PROC_NAME_MAX_LEN + 1];
|
||||||
|
void *pvt_info;
|
||||||
|
u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
|
||||||
|
u32 ce_noinfo_count; /* Correctable Errors w/o info */
|
||||||
|
u32 ue_count; /* Total Uncorrectable Errors for this MC */
|
||||||
|
u32 ce_count; /* Total Correctable Errors for this MC */
|
||||||
|
unsigned long start_time; /* mci load start time (in jiffies) */
|
||||||
|
|
||||||
|
struct completion complete;
|
||||||
|
|
||||||
|
/* edac sysfs device control */
|
||||||
|
struct kobject edac_mci_kobj;
|
||||||
|
|
||||||
|
/* list for all grp instances within a mc */
|
||||||
|
struct list_head grp_kobj_list;
|
||||||
|
|
||||||
|
/* Additional top controller level attributes, but specified
|
||||||
|
* by the low level driver.
|
||||||
|
*
|
||||||
|
* Set by the low level driver to provide attributes at the
|
||||||
|
* controller level, same level as 'ue_count' and 'ce_count' above.
|
||||||
|
* An array of structures, NULL terminated
|
||||||
|
*
|
||||||
|
* If attributes are desired, then set to array of attributes
|
||||||
|
* If no attributes are desired, leave NULL
|
||||||
|
*/
|
||||||
|
const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
|
||||||
|
|
||||||
|
/* work struct for this MC */
|
||||||
|
struct delayed_work work;
|
||||||
|
|
||||||
|
/* the internal state of this controller instance */
|
||||||
|
int op_state;
|
||||||
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue