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ARM: DT: Hisilicon ARMv7 SoC Hi3519 DT updates for 4.8 

- Add device tree bindings for hi3519 sysctrl
 - Add dts files for hi3519
 - Tidy up DTB makefile entries to keep the list sorted
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Merge tag 'hisi-armv7-soc-dt-for-4.8-v2' of git://github.com/hisilicon/linux-hisi into next/dt

Merge "ARM: DT: Hisilicon ARMv7 SoC Hi3519 DT updates for 4.8" from Wei Xu:

- Add device tree bindings for hi3519 sysctrl
- Add dts files for hi3519
- Tidy up DTB makefile entries to keep the list sorted

* tag 'hisi-armv7-soc-dt-for-4.8-v2' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: add dts files for Hi3519 and tidy up the makefile entries
  ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl
This commit is contained in:
Arnd Bergmann 2016-07-07 14:53:43 +02:00
parent 349f9d5239 747a1af0bb
commit dddaea6b96
4 changed files with 247 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt Normal file
View File

@ -0,0 +1,14 @@
* Hisilicon Hi3519 System Controller Block
This bindings use the following binding:
Documentation/devicetree/bindings/mfd/syscon.txt
Required properties:
- compatible: "hisilicon,hi3519-sysctrl".
- reg: the register region of this block
Examples:
sysctrl: system-controller@12010000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12010000 0x1000>;
};

6
arch/arm/boot/dts/Makefile
View File

@ -154,8 +154,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
highbank.dtb \
ecx-2000.dtb
@ -163,6 +161,10 @@ dtb-$(CONFIG_ARCH_HIP01) += \
hip01-ca9x2.dtb
dtb-$(CONFIG_ARCH_HIP04) += \
hip04-d01.dtb
dtb-$(CONFIG_ARCH_HISI) += \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
integratorcp.dtb

42
arch/arm/boot/dts/hi3519-demb.dts Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/dts-v1/;
#include "hi3519.dtsi"
/ {
model = "HiSilicon HI3519 DEMO Board";
compatible = "hisilicon,hi3519";
aliases {
serial0 = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};
&dual_timer0 {
status = "okay";
};

187
arch/arm/boot/dts/hi3519.dtsi Normal file
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@ -0,0 +1,187 @@
/*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <dt-bindings/clock/hi3519-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
};
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
};
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
crg: clock-reset-controller@12010000 {
compatible = "hisilicon,hi3519-crg";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x10000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
uart0: serial@12100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12100000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART0_CLK>;
clock-names = "apb_pclk";
status = "disable";
};
uart1: serial@12101000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12101000 0x1000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART1_CLK>;
clock-names = "apb_pclk";
status = "disable";
};
uart2: serial@12102000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12102000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART2_CLK>;
clock-names = "apb_pclk";
status = "disable";
};
uart3: serial@12103000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12103000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART3_CLK>;
clock-names = "apb_pclk";
status = "disable";
};
uart4: serial@12104000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12104000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_UART4_CLK>;
clock-names = "apb_pclk";
status = "disable";
};
dual_timer0: timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disable";
};
dual_timer1: timer@12001000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disable";
};
dual_timer2: timer@12002000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12002000 0x1000>;
clocks = <&clk_3m>;
clock-names = "apb_pclk";
status = "disable";
};
spi_bus0: spi@12120000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12120000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI0_CLK>;
clock-names = "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
};
spi_bus1: spi@12121000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12121000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI1_CLK>;
clock-names = "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
};
spi_bus2: spi@12122000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x12122000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3519_SPI2_CLK>;
clock-names = "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
};
sysctrl: system-controller@12020000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12020000 0x1000>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
};
};