Hexagon: Add locking types and functions
Signed-off-by: Richard Kuo <rkuo@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Richard Kuo
Linus Torvalds
parent
43afdf5083
commit
dd472da380
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/*
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* Spinlock support for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_SPINLOCK_H
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#define _ASM_SPINLOCK_H
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#include <asm/irqflags.h>
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/*
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* This file is pulled in for SMP builds.
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* Really need to check all the barrier stuff for "true" SMP
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*/
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/*
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* Read locks:
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* - load the lock value
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* - increment it
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* - if the lock value is still negative, go back and try again.
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* - unsuccessful store is unsuccessful. Go back and try again. Loser.
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* - successful store new lock value if positive -> lock acquired
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*/
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static inline void arch_read_lock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
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" { if !P3 jump 1b; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if !P3 jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline void arch_read_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" R6 = add(R6,#-1);\n"
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" memw_locked(%0,P3) = R6\n"
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" if !P3 jump 1b;\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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/* I think this returns 0 on fail, 1 on success. */
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static inline int arch_read_trylock(arch_rwlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1);\n"
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" { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
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" { if !P3 jump 1f; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" { %0 = P3 }\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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static inline int arch_read_can_lock(arch_rwlock_t *rwlock)
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{
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return rwlock->lock == 0;
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}
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static inline int arch_write_can_lock(arch_rwlock_t *rwlock)
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{
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return rwlock->lock == 0;
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}
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/* Stuffs a -1 in the lock value? */
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static inline void arch_write_lock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0)\n"
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" { P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
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" { if !P3 jump 1b; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if !P3 jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline int arch_write_trylock(arch_rwlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1)\n"
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" { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
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" { if !P3 jump 1f; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" %0 = P3;\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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static inline void arch_write_unlock(arch_rwlock_t *lock)
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{
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smp_mb();
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lock->lock = 0;
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}
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__(
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"1: R6 = memw_locked(%0);\n"
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" P3 = cmp.eq(R6,#0);\n"
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" { if !P3 jump 1b; R6 = #1; }\n"
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" memw_locked(%0,P3) = R6;\n"
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" { if !P3 jump 1b; }\n"
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:
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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lock->lock = 0;
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}
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static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
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{
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int temp;
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__asm__ __volatile__(
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" R6 = memw_locked(%1);\n"
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" P3 = cmp.eq(R6,#0);\n"
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" { if !P3 jump 1f; R6 = #1; %0 = #0; }\n"
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" memw_locked(%1,P3) = R6;\n"
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" %0 = P3;\n"
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"1:\n"
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: "=&r" (temp)
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: "r" (&lock->lock)
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: "memory", "r6", "p3"
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);
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return temp;
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}
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/*
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* SMP spinlocks are intended to allow only a single CPU at the lock
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*/
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_spin_unlock_wait(lock) \
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do {while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#endif
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@ -0,0 +1,42 @@
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/*
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* Spinlock support for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_SPINLOCK_TYPES_H
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#define _ASM_SPINLOCK_TYPES_H
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#include <linux/version.h>
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#ifndef __LINUX_SPINLOCK_TYPES_H
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# error "please don't include this file directly"
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#endif
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typedef struct {
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volatile unsigned int lock;
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} arch_spinlock_t;
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#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
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typedef struct {
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volatile unsigned int lock;
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} arch_rwlock_t;
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#define __ARCH_RW_LOCK_UNLOCKED { 0 }
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#endif
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#ifndef _ASM_POWERPC_RWSEM_H
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#define _ASM_POWERPC_RWSEM_H
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#ifndef _LINUX_RWSEM_H
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#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
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#endif
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#ifdef __KERNEL__
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/*
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* R/W semaphores for PPC using the stuff in lib/rwsem.c.
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* Adapted largely from include/asm-i386/rwsem.h
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* by Paul Mackerras <paulus@samba.org>.
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*/
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/*
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* the semaphore definition
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*/
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#ifdef CONFIG_PPC64
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# define RWSEM_ACTIVE_MASK 0xffffffffL
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#else
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# define RWSEM_ACTIVE_MASK 0x0000ffffL
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#endif
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#define RWSEM_UNLOCKED_VALUE 0x00000000L
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#define RWSEM_ACTIVE_BIAS 0x00000001L
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#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
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#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
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#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
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/*
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* lock for reading
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*/
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static inline void __down_read(struct rw_semaphore *sem)
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{
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if (unlikely(atomic_long_inc_return((atomic_long_t *)&sem->count) <= 0))
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rwsem_down_read_failed(sem);
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}
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static inline int __down_read_trylock(struct rw_semaphore *sem)
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{
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long tmp;
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while ((tmp = sem->count) >= 0) {
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if (tmp == cmpxchg(&sem->count, tmp,
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tmp + RWSEM_ACTIVE_READ_BIAS)) {
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return 1;
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}
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}
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return 0;
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}
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/*
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* lock for writing
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*/
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static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
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{
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long tmp;
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tmp = atomic_long_add_return(RWSEM_ACTIVE_WRITE_BIAS,
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(atomic_long_t *)&sem->count);
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if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
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rwsem_down_write_failed(sem);
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}
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static inline void __down_write(struct rw_semaphore *sem)
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{
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__down_write_nested(sem, 0);
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}
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static inline int __down_write_trylock(struct rw_semaphore *sem)
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{
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long tmp;
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tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
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RWSEM_ACTIVE_WRITE_BIAS);
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return tmp == RWSEM_UNLOCKED_VALUE;
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}
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/*
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* unlock after reading
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*/
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static inline void __up_read(struct rw_semaphore *sem)
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{
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long tmp;
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tmp = atomic_long_dec_return((atomic_long_t *)&sem->count);
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if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
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rwsem_wake(sem);
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}
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/*
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* unlock after writing
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*/
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static inline void __up_write(struct rw_semaphore *sem)
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{
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if (unlikely(atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
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(atomic_long_t *)&sem->count) < 0))
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rwsem_wake(sem);
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}
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/*
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* implement atomic add functionality
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*/
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static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
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{
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atomic_long_add(delta, (atomic_long_t *)&sem->count);
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}
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/*
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* downgrade write lock to read lock
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*/
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static inline void __downgrade_write(struct rw_semaphore *sem)
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{
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long tmp;
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tmp = atomic_long_add_return(-RWSEM_WAITING_BIAS,
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(atomic_long_t *)&sem->count);
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if (tmp < 0)
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rwsem_downgrade_wake(sem);
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}
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/*
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* implement exchange and add functionality
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*/
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static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
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{
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return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_RWSEM_H */
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