mailbox: Add Tegra HSP driver
This contains the device tree bindings and a driver for the Tegra HSP, a hardware block that provides hardware synchronization primitives and is the foundation for inter-processor communication between CPU and BPMP. -----BEGIN PGP SIGNATURE----- iQIwBAABCAAaBQJYLyMbExx0cmVkaW5nQG52aWRpYS5jb20ACgkQ3SOs138+s6El gw/9FfJG4Ze7thnBHHVhDDuZaVF6U9gIKkEHfTKkUlU8fkOtF+xnTBCK3LRkHEsk X0zyQlKKa/lzUGB52Fsi9jpVjt1WXvyuVOgCaQ+Zg9GXCmfXxOrNquAIH9sLhHSk SpBsVHDsCk5UT4pINJrmdpGN2nSdQ4PvsRZM8wRkRs39C7+nf6wSHMrjURCt/DLT Cub94gLcFiLddmO+c1OUShUjnOcy7yBIWn/EycxrKOqMDxzY9JK2Q0n8Cc3f1UVN P5WYgjvLss5pGWZOBvPwefMVXru7BFBh1jOceabueD3DjNEP8nWb2/WQbXMUDVzq QQ/q/4MIEmQMc8B8Z0brEmpIMn870Y3IPDaUmG4F6soW9yRL1gyA9PiF4YlcTe53 b0l0Y4/aehgHqCz1c9FulZW+qBe746fND/CNzTER7QfUe5CNotAtRUWG99v/8gGF gtVmwTVnC5jn4ytUbLHEM4JtghKUuoIHqAWhY7KdwTDOm70TLmdHmOTVKN0+Ej3V IgFCo+WIzleoHyK8GiUifOZSnLIJuctDznIUMnw2OmBlslvcdE90XbSQ00hlYC3N Z9N2X6747OhGZF6viHWdWOtFfH+LpRj4S0LIaoRkvU5GRUi0fOjuTIXfBhlPe+11 wZ/AZAav1CHfaJk66H7Vq2rmRxdwe56t9fzy/xJM7ja+9m0= =Gojp -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers mailbox: Add Tegra HSP driver This contains the device tree bindings and a driver for the Tegra HSP, a hardware block that provides hardware synchronization primitives and is the foundation for inter-processor communication between CPU and BPMP. * tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver dt-bindings: mailbox: Add Tegra HSP binding soc/tegra: Add Tegra186 support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
dd3eedd338
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@ -0,0 +1,52 @@
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NVIDIA Tegra Hardware Synchronization Primitives (HSP)
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The HSP modules are used for the processors to share resources and communicate
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together. It provides a set of hardware synchronization primitives for
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interprocessor communication. So the interprocessor communication (IPC)
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protocols can use hardware synchronization primitives, when operating between
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two processors not in an SMP relationship.
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The features that HSP supported are shared mailboxes, shared semaphores,
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arbitrated semaphores and doorbells.
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Required properties:
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- name : Should be hsp
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- compatible
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Array of strings.
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one of:
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- "nvidia,tegra186-hsp"
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- reg : Offset and length of the register set for the device.
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- interrupt-names
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Array of strings.
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Contains a list of names for the interrupts described by the interrupt
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property. May contain the following entries, in any order:
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- "doorbell"
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Users of this binding MUST look up entries in the interrupt property
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by name, using this interrupt-names property to do so.
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- interrupts
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Array of interrupt specifiers.
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Must contain one entry per entry in the interrupt-names property,
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in a matching order.
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- #mbox-cells : Should be 2.
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The mbox specifier of the "mboxes" property in the client node should
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contain two data. The first one should be the HSP type and the second
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one should be the ID that the client is going to use. Those information
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can be found in the following file.
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- <dt-bindings/mailbox/tegra186-hsp.h>.
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Example:
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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client {
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...
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
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};
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@ -124,6 +124,15 @@ config MAILBOX_TEST
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Test client to help with testing new Controller driver
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implementations.
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config TEGRA_HSP_MBOX
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bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
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depends on ARCH_TEGRA_186_SOC
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help
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The Tegra HSP driver is used for the interprocessor communication
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between different remote processors and host processors on Tegra186
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and later SoCs. Say Y here if you want to have this support.
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If unsure say N.
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config XGENE_SLIMPRO_MBOX
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tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
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depends on ARCH_XGENE
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@ -29,3 +29,5 @@ obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
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obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
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obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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@ -0,0 +1,479 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mailbox_controller.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#define HSP_INT_DIMENSIONING 0x380
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#define HSP_nSM_SHIFT 0
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#define HSP_nSS_SHIFT 4
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#define HSP_nAS_SHIFT 8
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#define HSP_nDB_SHIFT 12
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#define HSP_nSI_SHIFT 16
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#define HSP_nINT_MASK 0xf
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#define HSP_DB_TRIGGER 0x0
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#define HSP_DB_ENABLE 0x4
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#define HSP_DB_RAW 0x8
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#define HSP_DB_PENDING 0xc
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#define HSP_DB_CCPLEX 1
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#define HSP_DB_BPMP 3
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#define HSP_DB_MAX 7
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struct tegra_hsp_channel;
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struct tegra_hsp;
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struct tegra_hsp_channel {
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struct tegra_hsp *hsp;
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struct mbox_chan *chan;
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void __iomem *regs;
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};
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struct tegra_hsp_doorbell {
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struct tegra_hsp_channel channel;
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struct list_head list;
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const char *name;
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unsigned int master;
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unsigned int index;
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};
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struct tegra_hsp_db_map {
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const char *name;
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unsigned int master;
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unsigned int index;
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};
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struct tegra_hsp_soc {
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const struct tegra_hsp_db_map *map;
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};
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struct tegra_hsp {
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const struct tegra_hsp_soc *soc;
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struct mbox_controller mbox;
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void __iomem *regs;
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unsigned int irq;
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unsigned int num_sm;
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unsigned int num_as;
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unsigned int num_ss;
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unsigned int num_db;
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unsigned int num_si;
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spinlock_t lock;
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struct list_head doorbells;
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};
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static inline struct tegra_hsp *
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to_tegra_hsp(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct tegra_hsp, mbox);
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}
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static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
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{
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return readl(hsp->regs + offset);
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}
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static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
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unsigned int offset)
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{
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writel(value, hsp->regs + offset);
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}
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static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
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unsigned int offset)
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{
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return readl(channel->regs + offset);
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}
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static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
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u32 value, unsigned int offset)
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{
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writel(value, channel->regs + offset);
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}
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static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
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{
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u32 value;
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value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
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return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
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}
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static struct tegra_hsp_doorbell *
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__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
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{
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struct tegra_hsp_doorbell *entry;
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list_for_each_entry(entry, &hsp->doorbells, list)
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if (entry->master == master)
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return entry;
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return NULL;
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}
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static struct tegra_hsp_doorbell *
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tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
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{
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struct tegra_hsp_doorbell *db;
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unsigned long flags;
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spin_lock_irqsave(&hsp->lock, flags);
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db = __tegra_hsp_doorbell_get(hsp, master);
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spin_unlock_irqrestore(&hsp->lock, flags);
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return db;
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}
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static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
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{
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struct tegra_hsp *hsp = data;
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struct tegra_hsp_doorbell *db;
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unsigned long master, value;
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db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
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if (!db)
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return IRQ_NONE;
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value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
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tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
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spin_lock(&hsp->lock);
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for_each_set_bit(master, &value, hsp->mbox.num_chans) {
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struct tegra_hsp_doorbell *db;
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db = __tegra_hsp_doorbell_get(hsp, master);
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/*
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* Depending on the bootloader chain, the CCPLEX doorbell will
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* have some doorbells enabled, which means that requesting an
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* interrupt will immediately fire.
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*
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* In that case, db->channel.chan will still be NULL here and
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* cause a crash if not properly guarded.
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*
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* It remains to be seen if ignoring the doorbell in that case
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* is the correct solution.
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*/
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if (db && db->channel.chan)
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mbox_chan_received_data(db->channel.chan, NULL);
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}
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spin_unlock(&hsp->lock);
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return IRQ_HANDLED;
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}
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static struct tegra_hsp_channel *
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tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
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unsigned int master, unsigned int index)
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{
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struct tegra_hsp_doorbell *db;
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unsigned int offset;
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unsigned long flags;
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db = kzalloc(sizeof(*db), GFP_KERNEL);
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if (!db)
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return ERR_PTR(-ENOMEM);
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offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16;
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offset += index * 0x100;
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db->channel.regs = hsp->regs + offset;
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db->channel.hsp = hsp;
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db->name = kstrdup_const(name, GFP_KERNEL);
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db->master = master;
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db->index = index;
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spin_lock_irqsave(&hsp->lock, flags);
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list_add_tail(&db->list, &hsp->doorbells);
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spin_unlock_irqrestore(&hsp->lock, flags);
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return &db->channel;
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}
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static void __tegra_hsp_doorbell_destroy(struct tegra_hsp_doorbell *db)
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{
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list_del(&db->list);
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kfree_const(db->name);
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kfree(db);
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}
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static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
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{
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struct tegra_hsp_doorbell *db = chan->con_priv;
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tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
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return 0;
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}
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static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
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{
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struct tegra_hsp_doorbell *db = chan->con_priv;
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struct tegra_hsp *hsp = db->channel.hsp;
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struct tegra_hsp_doorbell *ccplex;
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unsigned long flags;
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u32 value;
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if (db->master >= hsp->mbox.num_chans) {
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dev_err(hsp->mbox.dev,
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"invalid master ID %u for HSP channel\n",
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db->master);
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return -EINVAL;
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}
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ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
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if (!ccplex)
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return -ENODEV;
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if (!tegra_hsp_doorbell_can_ring(db))
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return -ENODEV;
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spin_lock_irqsave(&hsp->lock, flags);
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value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
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value |= BIT(db->master);
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tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
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spin_unlock_irqrestore(&hsp->lock, flags);
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return 0;
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}
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static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
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{
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struct tegra_hsp_doorbell *db = chan->con_priv;
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struct tegra_hsp *hsp = db->channel.hsp;
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struct tegra_hsp_doorbell *ccplex;
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unsigned long flags;
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u32 value;
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ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
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if (!ccplex)
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return;
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spin_lock_irqsave(&hsp->lock, flags);
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value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
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value &= ~BIT(db->master);
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tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
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spin_unlock_irqrestore(&hsp->lock, flags);
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}
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static const struct mbox_chan_ops tegra_hsp_doorbell_ops = {
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.send_data = tegra_hsp_doorbell_send_data,
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.startup = tegra_hsp_doorbell_startup,
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.shutdown = tegra_hsp_doorbell_shutdown,
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};
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static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *args)
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{
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struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
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struct tegra_hsp *hsp = to_tegra_hsp(mbox);
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unsigned int type = args->args[0];
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unsigned int master = args->args[1];
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struct tegra_hsp_doorbell *db;
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struct mbox_chan *chan;
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unsigned long flags;
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unsigned int i;
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switch (type) {
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case TEGRA_HSP_MBOX_TYPE_DB:
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db = tegra_hsp_doorbell_get(hsp, master);
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if (db)
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channel = &db->channel;
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break;
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default:
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break;
|
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}
|
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if (IS_ERR(channel))
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return ERR_CAST(channel);
|
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|
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spin_lock_irqsave(&hsp->lock, flags);
|
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|
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for (i = 0; i < hsp->mbox.num_chans; i++) {
|
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chan = &hsp->mbox.chans[i];
|
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if (!chan->con_priv) {
|
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chan->con_priv = channel;
|
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channel->chan = chan;
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break;
|
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}
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chan = NULL;
|
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}
|
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|
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spin_unlock_irqrestore(&hsp->lock, flags);
|
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|
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return chan ?: ERR_PTR(-EBUSY);
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}
|
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|
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static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp)
|
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{
|
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struct tegra_hsp_doorbell *db, *tmp;
|
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unsigned long flags;
|
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|
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spin_lock_irqsave(&hsp->lock, flags);
|
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|
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list_for_each_entry_safe(db, tmp, &hsp->doorbells, list)
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__tegra_hsp_doorbell_destroy(db);
|
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|
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spin_unlock_irqrestore(&hsp->lock, flags);
|
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}
|
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|
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static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
|
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{
|
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const struct tegra_hsp_db_map *map = hsp->soc->map;
|
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struct tegra_hsp_channel *channel;
|
||||
|
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while (map->name) {
|
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channel = tegra_hsp_doorbell_create(hsp, map->name,
|
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map->master, map->index);
|
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if (IS_ERR(channel)) {
|
||||
tegra_hsp_remove_doorbells(hsp);
|
||||
return PTR_ERR(channel);
|
||||
}
|
||||
|
||||
map++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_hsp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_hsp *hsp;
|
||||
struct resource *res;
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
|
||||
if (!hsp)
|
||||
return -ENOMEM;
|
||||
|
||||
hsp->soc = of_device_get_match_data(&pdev->dev);
|
||||
INIT_LIST_HEAD(&hsp->doorbells);
|
||||
spin_lock_init(&hsp->lock);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hsp->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(hsp->regs))
|
||||
return PTR_ERR(hsp->regs);
|
||||
|
||||
value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
|
||||
hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
|
||||
hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
|
||||
hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
|
||||
hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
|
||||
hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
|
||||
|
||||
err = platform_get_irq_byname(pdev, "doorbell");
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
hsp->irq = err;
|
||||
|
||||
hsp->mbox.of_xlate = of_tegra_hsp_xlate;
|
||||
hsp->mbox.num_chans = 32;
|
||||
hsp->mbox.dev = &pdev->dev;
|
||||
hsp->mbox.txdone_irq = false;
|
||||
hsp->mbox.txdone_poll = false;
|
||||
hsp->mbox.ops = &tegra_hsp_doorbell_ops;
|
||||
|
||||
hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans,
|
||||
sizeof(*hsp->mbox.chans),
|
||||
GFP_KERNEL);
|
||||
if (!hsp->mbox.chans)
|
||||
return -ENOMEM;
|
||||
|
||||
err = tegra_hsp_add_doorbells(hsp);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to add doorbells: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, hsp);
|
||||
|
||||
err = mbox_controller_register(&hsp->mbox);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to register mailbox: %d\n", err);
|
||||
tegra_hsp_remove_doorbells(hsp);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq,
|
||||
IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
|
||||
hsp->irq, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_hsp_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_hsp *hsp = platform_get_drvdata(pdev);
|
||||
|
||||
mbox_controller_unregister(&hsp->mbox);
|
||||
tegra_hsp_remove_doorbells(hsp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
|
||||
{ "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
|
||||
{ "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct tegra_hsp_soc tegra186_hsp_soc = {
|
||||
.map = tegra186_hsp_db_map,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_hsp_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver tegra_hsp_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-hsp",
|
||||
.of_match_table = tegra_hsp_match,
|
||||
},
|
||||
.probe = tegra_hsp_probe,
|
||||
.remove = tegra_hsp_remove,
|
||||
};
|
||||
|
||||
static int __init tegra_hsp_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_hsp_driver);
|
||||
}
|
||||
core_initcall(tegra_hsp_init);
|
||||
|
|
@ -77,5 +77,19 @@ config ARCH_TEGRA_210_SOC
|
|||
controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
|
||||
name only a few.
|
||||
|
||||
config ARCH_TEGRA_186_SOC
|
||||
bool "NVIDIA Tegra186 SoC"
|
||||
select MAILBOX
|
||||
select TEGRA_BPMP
|
||||
select TEGRA_HSP_MBOX
|
||||
select TEGRA_IVC
|
||||
help
|
||||
Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
|
||||
combination of Denver and Cortex-A57 CPU cores and a GPU based on
|
||||
the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
|
||||
used for audio processing, hardware video encoders/decoders with
|
||||
multi-format support, ISP for image capture processing and BPMP for
|
||||
power management.
|
||||
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra186-hsp.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
|
||||
#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
|
||||
|
||||
/*
|
||||
* These define the type of mailbox that is to be used (doorbell, shared
|
||||
* mailbox, shared semaphore or arbitrated semaphore).
|
||||
*/
|
||||
#define TEGRA_HSP_MBOX_TYPE_DB 0x0
|
||||
#define TEGRA_HSP_MBOX_TYPE_SM 0x1
|
||||
#define TEGRA_HSP_MBOX_TYPE_SS 0x2
|
||||
#define TEGRA_HSP_MBOX_TYPE_AS 0x3
|
||||
|
||||
/*
|
||||
* These defines represent the bit associated with the given master ID in the
|
||||
* doorbell registers.
|
||||
*/
|
||||
#define TEGRA_HSP_DB_MASTER_CCPLEX 17
|
||||
#define TEGRA_HSP_DB_MASTER_BPMP 19
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue