i40e: separate TSYNVALID and TSYNINDX fields in Rx descriptor
In order to get 1588 to work correctly the defines need a bit of a tweak. Change-Id: Ie50ce2a18e1593441f1560411e5a4f51c6d48aaa Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -500,7 +500,8 @@ enum i40e_rx_desc_status_bits {
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I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
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I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
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I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
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I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 3 BITS */
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I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
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I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
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I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
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I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
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I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
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@ -509,9 +510,13 @@ enum i40e_rx_desc_status_bits {
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};
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#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
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#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x7UL << \
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#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
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I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
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#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
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#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
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I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
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enum i40e_rx_desc_fltstat_values {
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I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
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I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
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