Merge branch 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6
* 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6: cpuidle/x86/perf: fix power:cpu_idle double end events and throw cpu_idle events from the cpuidle layer intel_idle: open broadcast clock event cpuidle: CPUIDLE_FLAG_CHECK_BM is omap3_idle specific cpuidle: CPUIDLE_FLAG_TLB_FLUSHED is specific to intel_idle cpuidle: delete unused CPUIDLE_FLAG_SHALLOW, BALANCED, DEEP definitions SH, cpuidle: delete use of NOP CPUIDLE_FLAGS_SHALLOW cpuidle: delete NOP CPUIDLE_FLAG_POLL ACPI: processor_idle: delete use of NOP CPUIDLE_FLAGs cpuidle: Rename X86 specific idle poll state[0] from C0 to POLL ACPI, intel_idle: Cleanup idle= internal variables cpuidle: Make cpuidle_enable_device() call poll_idle_init() intel_idle: update Sandy Bridge core C-state residency targets
This commit is contained in:
commit
dc8e7e3ec6
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@ -47,6 +47,8 @@
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#define OMAP3_STATE_MAX OMAP3_STATE_C7
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#define CPUIDLE_FLAG_CHECK_BM 0x10000 /* use omap3_enter_idle_bm() */
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struct omap3_processor_cx {
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u8 valid;
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u8 type;
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@ -717,8 +717,9 @@ prefetchw (const void *x)
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#define spin_lock_prefetch(x) prefetchw(x)
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extern unsigned long boot_option_idle_override;
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extern unsigned long idle_halt;
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extern unsigned long idle_nomwait;
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enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
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IDLE_NOMWAIT, IDLE_POLL};
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#endif /* !__ASSEMBLY__ */
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@ -53,12 +53,8 @@
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void (*ia64_mark_idle)(int);
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unsigned long boot_option_idle_override = 0;
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unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
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EXPORT_SYMBOL(boot_option_idle_override);
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unsigned long idle_halt;
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EXPORT_SYMBOL(idle_halt);
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unsigned long idle_nomwait;
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EXPORT_SYMBOL(idle_nomwait);
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void (*pm_idle) (void);
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EXPORT_SYMBOL(pm_idle);
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void (*pm_power_off) (void);
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@ -81,7 +81,6 @@ void sh_mobile_setup_cpuidle(void)
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state->target_residency = 1 * 2;
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state->power_usage = 3;
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state->flags = 0;
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state->flags |= CPUIDLE_FLAG_SHALLOW;
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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state->enter = cpuidle_sleep_enter;
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@ -761,10 +761,11 @@ extern void select_idle_routine(const struct cpuinfo_x86 *c);
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extern void init_c1e_mask(void);
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extern unsigned long boot_option_idle_override;
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extern unsigned long idle_halt;
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extern unsigned long idle_nomwait;
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extern bool c1e_detected;
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enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
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IDLE_POLL, IDLE_FORCE_MWAIT};
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extern void enable_sep_cpu(void);
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extern int sysenter_setup(void);
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@ -22,11 +22,6 @@
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#include <asm/i387.h>
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#include <asm/debugreg.h>
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unsigned long idle_halt;
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EXPORT_SYMBOL(idle_halt);
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unsigned long idle_nomwait;
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EXPORT_SYMBOL(idle_nomwait);
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struct kmem_cache *task_xstate_cachep;
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EXPORT_SYMBOL_GPL(task_xstate_cachep);
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@ -327,7 +322,7 @@ long sys_execve(const char __user *name,
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/*
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* Idle related variables and functions
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*/
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unsigned long boot_option_idle_override = 0;
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unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
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EXPORT_SYMBOL(boot_option_idle_override);
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/*
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@ -386,6 +381,8 @@ void default_idle(void)
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else
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local_irq_enable();
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current_thread_info()->status |= TS_POLLING;
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trace_power_end(smp_processor_id());
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trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
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} else {
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local_irq_enable();
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/* loop is done by the caller */
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@ -443,8 +440,6 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait);
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*/
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void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
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{
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trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id());
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trace_cpu_idle((ax>>4)+1, smp_processor_id());
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if (!need_resched()) {
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if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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|
@ -471,6 +466,8 @@ static void mwait_idle(void)
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__sti_mwait(0, 0);
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else
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local_irq_enable();
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trace_power_end(smp_processor_id());
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trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
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} else
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local_irq_enable();
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}
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|
@ -503,7 +500,6 @@ static void poll_idle(void)
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*
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* idle=mwait overrides this decision and forces the usage of mwait.
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*/
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static int __cpuinitdata force_mwait;
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#define MWAIT_INFO 0x05
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#define MWAIT_ECX_EXTENDED_INFO 0x01
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|
@ -513,7 +509,7 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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if (force_mwait)
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if (boot_option_idle_override == IDLE_FORCE_MWAIT)
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return 1;
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if (c->cpuid_level < MWAIT_INFO)
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|
@ -633,9 +629,10 @@ static int __init idle_setup(char *str)
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if (!strcmp(str, "poll")) {
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printk("using polling idle threads.\n");
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pm_idle = poll_idle;
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} else if (!strcmp(str, "mwait"))
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force_mwait = 1;
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else if (!strcmp(str, "halt")) {
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boot_option_idle_override = IDLE_POLL;
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} else if (!strcmp(str, "mwait")) {
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boot_option_idle_override = IDLE_FORCE_MWAIT;
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} else if (!strcmp(str, "halt")) {
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/*
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* When the boot option of idle=halt is added, halt is
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* forced to be used for CPU idle. In such case CPU C2/C3
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@ -644,8 +641,7 @@ static int __init idle_setup(char *str)
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* the boot_option_idle_override.
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*/
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pm_idle = default_idle;
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idle_halt = 1;
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return 0;
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boot_option_idle_override = IDLE_HALT;
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} else if (!strcmp(str, "nomwait")) {
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/*
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* If the boot option of "idle=nomwait" is added,
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|
@ -653,12 +649,10 @@ static int __init idle_setup(char *str)
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* states. In such case it won't touch the variable
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* of boot_option_idle_override.
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*/
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idle_nomwait = 1;
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return 0;
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boot_option_idle_override = IDLE_NOMWAIT;
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} else
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return -1;
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boot_option_idle_override = 1;
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return 0;
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}
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early_param("idle", idle_setup);
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|
@ -57,8 +57,6 @@
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#include <asm/syscalls.h>
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#include <asm/debugreg.h>
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#include <trace/events/power.h>
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asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
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/*
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@ -113,8 +111,6 @@ void cpu_idle(void)
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stop_critical_timings();
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pm_idle();
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start_critical_timings();
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trace_power_end(smp_processor_id());
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trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
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}
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tick_nohz_restart_sched_tick();
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preempt_enable_no_resched();
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|
@ -51,8 +51,6 @@
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#include <asm/syscalls.h>
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#include <asm/debugreg.h>
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#include <trace/events/power.h>
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asmlinkage extern void ret_from_fork(void);
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DEFINE_PER_CPU(unsigned long, old_rsp);
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|
@ -141,10 +139,6 @@ void cpu_idle(void)
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pm_idle();
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start_critical_timings();
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trace_power_end(smp_processor_id());
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trace_cpu_idle(PWR_EVENT_EXIT,
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smp_processor_id());
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/* In many cases the interrupt that ended idle
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has already called exit_idle. But some idle
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loops can be woken up without interrupt. */
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@ -23,7 +23,7 @@ static int set_no_mwait(const struct dmi_system_id *id)
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{
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printk(KERN_NOTICE PREFIX "%s detected - "
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"disabling mwait for CPU C-states\n", id->ident);
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idle_nomwait = 1;
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boot_option_idle_override = IDLE_NOMWAIT;
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return 0;
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}
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|
@ -283,7 +283,7 @@ acpi_processor_eval_pdc(acpi_handle handle, struct acpi_object_list *pdc_in)
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{
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acpi_status status = AE_OK;
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if (idle_nomwait) {
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if (boot_option_idle_override == IDLE_NOMWAIT) {
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/*
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* If mwait is disabled for CPU C-states, the C2C3_FFH access
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* mode will be disabled in the parameter of _PDC object.
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|
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|
@ -79,6 +79,13 @@ module_param(bm_check_disable, uint, 0000);
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static unsigned int latency_factor __read_mostly = 2;
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module_param(latency_factor, uint, 0644);
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static int disabled_by_idle_boot_param(void)
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{
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return boot_option_idle_override == IDLE_POLL ||
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boot_option_idle_override == IDLE_FORCE_MWAIT ||
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boot_option_idle_override == IDLE_HALT;
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}
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/*
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* IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
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* For now disable this. Probably a bug somewhere else.
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|
@ -455,7 +462,7 @@ static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
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continue;
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}
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if (cx.type == ACPI_STATE_C1 &&
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(idle_halt || idle_nomwait)) {
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(boot_option_idle_override == IDLE_NOMWAIT)) {
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/*
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* In most cases the C1 space_id obtained from
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* _CST object is FIXED_HARDWARE access mode.
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|
@ -1016,7 +1023,6 @@ static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
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state->flags = 0;
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switch (cx->type) {
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case ACPI_STATE_C1:
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state->flags |= CPUIDLE_FLAG_SHALLOW;
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if (cx->entry_method == ACPI_CSTATE_FFH)
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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|
@ -1025,16 +1031,13 @@ static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
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break;
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case ACPI_STATE_C2:
|
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state->flags |= CPUIDLE_FLAG_BALANCED;
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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state->enter = acpi_idle_enter_simple;
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dev->safe_state = state;
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break;
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|
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case ACPI_STATE_C3:
|
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state->flags |= CPUIDLE_FLAG_DEEP;
|
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
|
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state->flags |= CPUIDLE_FLAG_CHECK_BM;
|
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state->enter = pr->flags.bm_check ?
|
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acpi_idle_enter_bm :
|
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acpi_idle_enter_simple;
|
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|
@ -1058,7 +1061,7 @@ int acpi_processor_cst_has_changed(struct acpi_processor *pr)
|
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{
|
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int ret = 0;
|
||||
|
||||
if (boot_option_idle_override)
|
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if (disabled_by_idle_boot_param())
|
||||
return 0;
|
||||
|
||||
if (!pr)
|
||||
|
@ -1089,19 +1092,10 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
|
|||
acpi_status status = 0;
|
||||
static int first_run;
|
||||
|
||||
if (boot_option_idle_override)
|
||||
if (disabled_by_idle_boot_param())
|
||||
return 0;
|
||||
|
||||
if (!first_run) {
|
||||
if (idle_halt) {
|
||||
/*
|
||||
* When the boot option of "idle=halt" is added, halt
|
||||
* is used for CPU IDLE.
|
||||
* In such case C2/C3 is meaningless. So the max_cstate
|
||||
* is set to one.
|
||||
*/
|
||||
max_cstate = 1;
|
||||
}
|
||||
dmi_check_system(processor_power_dmi_table);
|
||||
max_cstate = acpi_processor_cstate_check(max_cstate);
|
||||
if (max_cstate < ACPI_C_STATES_MAX)
|
||||
|
@ -1142,7 +1136,7 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
|
|||
int acpi_processor_power_exit(struct acpi_processor *pr,
|
||||
struct acpi_device *device)
|
||||
{
|
||||
if (boot_option_idle_override)
|
||||
if (disabled_by_idle_boot_param())
|
||||
return 0;
|
||||
|
||||
cpuidle_unregister_device(&pr->power.dev);
|
||||
|
|
|
@ -96,7 +96,15 @@ static void cpuidle_idle_call(void)
|
|||
|
||||
/* enter the state and update stats */
|
||||
dev->last_state = target_state;
|
||||
|
||||
trace_power_start(POWER_CSTATE, next_state, dev->cpu);
|
||||
trace_cpu_idle(next_state, dev->cpu);
|
||||
|
||||
dev->last_residency = target_state->enter(dev, target_state);
|
||||
|
||||
trace_power_end(dev->cpu);
|
||||
trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
|
||||
|
||||
if (dev->last_state)
|
||||
target_state = dev->last_state;
|
||||
|
||||
|
@ -106,8 +114,6 @@ static void cpuidle_idle_call(void)
|
|||
/* give the governor an opportunity to reflect on the outcome */
|
||||
if (cpuidle_curr_governor->reflect)
|
||||
cpuidle_curr_governor->reflect(dev);
|
||||
trace_power_end(smp_processor_id());
|
||||
trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -155,6 +161,45 @@ void cpuidle_resume_and_unlock(void)
|
|||
|
||||
EXPORT_SYMBOL_GPL(cpuidle_resume_and_unlock);
|
||||
|
||||
#ifdef CONFIG_ARCH_HAS_CPU_RELAX
|
||||
static int poll_idle(struct cpuidle_device *dev, struct cpuidle_state *st)
|
||||
{
|
||||
ktime_t t1, t2;
|
||||
s64 diff;
|
||||
int ret;
|
||||
|
||||
t1 = ktime_get();
|
||||
local_irq_enable();
|
||||
while (!need_resched())
|
||||
cpu_relax();
|
||||
|
||||
t2 = ktime_get();
|
||||
diff = ktime_to_us(ktime_sub(t2, t1));
|
||||
if (diff > INT_MAX)
|
||||
diff = INT_MAX;
|
||||
|
||||
ret = (int) diff;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void poll_idle_init(struct cpuidle_device *dev)
|
||||
{
|
||||
struct cpuidle_state *state = &dev->states[0];
|
||||
|
||||
cpuidle_set_statedata(state, NULL);
|
||||
|
||||
snprintf(state->name, CPUIDLE_NAME_LEN, "POLL");
|
||||
snprintf(state->desc, CPUIDLE_DESC_LEN, "CPUIDLE CORE POLL IDLE");
|
||||
state->exit_latency = 0;
|
||||
state->target_residency = 0;
|
||||
state->power_usage = -1;
|
||||
state->flags = 0;
|
||||
state->enter = poll_idle;
|
||||
}
|
||||
#else
|
||||
static void poll_idle_init(struct cpuidle_device *dev) {}
|
||||
#endif /* CONFIG_ARCH_HAS_CPU_RELAX */
|
||||
|
||||
/**
|
||||
* cpuidle_enable_device - enables idle PM for a CPU
|
||||
* @dev: the CPU
|
||||
|
@ -179,6 +224,8 @@ int cpuidle_enable_device(struct cpuidle_device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
poll_idle_init(dev);
|
||||
|
||||
if ((ret = cpuidle_add_state_sysfs(dev)))
|
||||
return ret;
|
||||
|
||||
|
@ -233,45 +280,6 @@ void cpuidle_disable_device(struct cpuidle_device *dev)
|
|||
|
||||
EXPORT_SYMBOL_GPL(cpuidle_disable_device);
|
||||
|
||||
#ifdef CONFIG_ARCH_HAS_CPU_RELAX
|
||||
static int poll_idle(struct cpuidle_device *dev, struct cpuidle_state *st)
|
||||
{
|
||||
ktime_t t1, t2;
|
||||
s64 diff;
|
||||
int ret;
|
||||
|
||||
t1 = ktime_get();
|
||||
local_irq_enable();
|
||||
while (!need_resched())
|
||||
cpu_relax();
|
||||
|
||||
t2 = ktime_get();
|
||||
diff = ktime_to_us(ktime_sub(t2, t1));
|
||||
if (diff > INT_MAX)
|
||||
diff = INT_MAX;
|
||||
|
||||
ret = (int) diff;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void poll_idle_init(struct cpuidle_device *dev)
|
||||
{
|
||||
struct cpuidle_state *state = &dev->states[0];
|
||||
|
||||
cpuidle_set_statedata(state, NULL);
|
||||
|
||||
snprintf(state->name, CPUIDLE_NAME_LEN, "C0");
|
||||
snprintf(state->desc, CPUIDLE_DESC_LEN, "CPUIDLE CORE POLL IDLE");
|
||||
state->exit_latency = 0;
|
||||
state->target_residency = 0;
|
||||
state->power_usage = -1;
|
||||
state->flags = CPUIDLE_FLAG_POLL;
|
||||
state->enter = poll_idle;
|
||||
}
|
||||
#else
|
||||
static void poll_idle_init(struct cpuidle_device *dev) {}
|
||||
#endif /* CONFIG_ARCH_HAS_CPU_RELAX */
|
||||
|
||||
/**
|
||||
* __cpuidle_register_device - internal register function called before register
|
||||
* and enable routines
|
||||
|
@ -292,8 +300,6 @@ static int __cpuidle_register_device(struct cpuidle_device *dev)
|
|||
|
||||
init_completion(&dev->kobj_unregister);
|
||||
|
||||
poll_idle_init(dev);
|
||||
|
||||
/*
|
||||
* cpuidle driver should set the dev->power_specified bit
|
||||
* before registering the device if the driver provides
|
||||
|
|
|
@ -59,6 +59,8 @@
|
|||
#include <linux/hrtimer.h> /* ktime_get_real() */
|
||||
#include <trace/events/power.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <asm/mwait.h>
|
||||
|
||||
#define INTEL_IDLE_VERSION "0.4"
|
||||
|
@ -73,6 +75,7 @@ static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
|
|||
|
||||
static unsigned int mwait_substates;
|
||||
|
||||
#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
|
||||
/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
|
||||
static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
|
||||
|
||||
|
@ -81,6 +84,14 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
|
|||
|
||||
static struct cpuidle_state *cpuidle_state_table;
|
||||
|
||||
/*
|
||||
* Set this flag for states where the HW flushes the TLB for us
|
||||
* and so we don't need cross-calls to keep it consistent.
|
||||
* If this flag is set, SW flushes the TLB, so even if the
|
||||
* HW doesn't do the flushing, this flag is safe to use.
|
||||
*/
|
||||
#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
|
||||
|
||||
/*
|
||||
* States are indexed by the cstate number,
|
||||
* which is also the index into the MWAIT hint array.
|
||||
|
@ -122,7 +133,7 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
|
|||
.driver_data = (void *) 0x00,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.exit_latency = 1,
|
||||
.target_residency = 4,
|
||||
.target_residency = 1,
|
||||
.enter = &intel_idle },
|
||||
{ /* MWAIT C2 */
|
||||
.name = "SNB-C3",
|
||||
|
@ -130,7 +141,7 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
|
|||
.driver_data = (void *) 0x10,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 80,
|
||||
.target_residency = 160,
|
||||
.target_residency = 211,
|
||||
.enter = &intel_idle },
|
||||
{ /* MWAIT C3 */
|
||||
.name = "SNB-C6",
|
||||
|
@ -138,7 +149,7 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
|
|||
.driver_data = (void *) 0x20,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 104,
|
||||
.target_residency = 208,
|
||||
.target_residency = 345,
|
||||
.enter = &intel_idle },
|
||||
{ /* MWAIT C4 */
|
||||
.name = "SNB-C7",
|
||||
|
@ -146,7 +157,7 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
|
|||
.driver_data = (void *) 0x30,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
|
||||
.exit_latency = 109,
|
||||
.target_residency = 300,
|
||||
.target_residency = 345,
|
||||
.enter = &intel_idle },
|
||||
};
|
||||
|
||||
|
@ -220,8 +231,6 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
|
|||
kt_before = ktime_get_real();
|
||||
|
||||
stop_critical_timings();
|
||||
trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
|
||||
trace_cpu_idle((eax >> 4) + 1, cpu);
|
||||
if (!need_resched()) {
|
||||
|
||||
__monitor((void *)¤t_thread_info()->flags, 0, 0);
|
||||
|
@ -243,6 +252,39 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
|
|||
return usec_delta;
|
||||
}
|
||||
|
||||
static void __setup_broadcast_timer(void *arg)
|
||||
{
|
||||
unsigned long reason = (unsigned long)arg;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
reason = reason ?
|
||||
CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
|
||||
|
||||
clockevents_notify(reason, &cpu);
|
||||
}
|
||||
|
||||
static int __cpuinit setup_broadcast_cpuhp_notify(struct notifier_block *n,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
int hotcpu = (unsigned long)hcpu;
|
||||
|
||||
switch (action & 0xf) {
|
||||
case CPU_ONLINE:
|
||||
smp_call_function_single(hotcpu, __setup_broadcast_timer,
|
||||
(void *)true, 1);
|
||||
break;
|
||||
case CPU_DOWN_PREPARE:
|
||||
smp_call_function_single(hotcpu, __setup_broadcast_timer,
|
||||
(void *)false, 1);
|
||||
break;
|
||||
}
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block __cpuinitdata setup_broadcast_notifier = {
|
||||
.notifier_call = setup_broadcast_cpuhp_notify,
|
||||
};
|
||||
|
||||
/*
|
||||
* intel_idle_probe()
|
||||
*/
|
||||
|
@ -305,7 +347,11 @@ static int intel_idle_probe(void)
|
|||
}
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
|
||||
lapic_timer_reliable_states = 0xFFFFFFFF;
|
||||
lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
|
||||
else {
|
||||
smp_call_function(__setup_broadcast_timer, (void *)true, 1);
|
||||
register_cpu_notifier(&setup_broadcast_notifier);
|
||||
}
|
||||
|
||||
pr_debug(PREFIX "v" INTEL_IDLE_VERSION
|
||||
" model 0x%X\n", boot_cpu_data.x86_model);
|
||||
|
@ -403,6 +449,10 @@ static int __init intel_idle_init(void)
|
|||
{
|
||||
int retval;
|
||||
|
||||
/* Do not load intel_idle at all for now if idle= is passed */
|
||||
if (boot_option_idle_override != IDLE_NO_OVERRIDE)
|
||||
return -ENODEV;
|
||||
|
||||
retval = intel_idle_probe();
|
||||
if (retval)
|
||||
return retval;
|
||||
|
@ -428,6 +478,11 @@ static void __exit intel_idle_exit(void)
|
|||
intel_idle_cpuidle_devices_uninit();
|
||||
cpuidle_unregister_driver(&intel_idle_driver);
|
||||
|
||||
if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
|
||||
smp_call_function(__setup_broadcast_timer, (void *)false, 1);
|
||||
unregister_cpu_notifier(&setup_broadcast_notifier);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -47,13 +47,7 @@ struct cpuidle_state {
|
|||
|
||||
/* Idle State Flags */
|
||||
#define CPUIDLE_FLAG_TIME_VALID (0x01) /* is residency time measurable? */
|
||||
#define CPUIDLE_FLAG_CHECK_BM (0x02) /* BM activity will exit state */
|
||||
#define CPUIDLE_FLAG_POLL (0x10) /* no latency, no savings */
|
||||
#define CPUIDLE_FLAG_SHALLOW (0x20) /* low latency, minimal savings */
|
||||
#define CPUIDLE_FLAG_BALANCED (0x40) /* medium latency, moderate savings */
|
||||
#define CPUIDLE_FLAG_DEEP (0x80) /* high latency, large savings */
|
||||
#define CPUIDLE_FLAG_IGNORE (0x100) /* ignore during this idle period */
|
||||
#define CPUIDLE_FLAG_TLB_FLUSHED (0x200) /* tlb will be flushed */
|
||||
|
||||
#define CPUIDLE_DRIVER_FLAGS_MASK (0xFFFF0000)
|
||||
|
||||
|
|
Loading…
Reference in New Issue