Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
5369fba136
commit
dc7101bbae
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@ -5,13 +5,13 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
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* - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
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*/
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/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
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@ -24,6 +24,8 @@
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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@ -52,6 +54,8 @@
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#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (1)
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
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/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
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@ -74,14 +78,21 @@
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (1)
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000119 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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@ -94,6 +105,7 @@
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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@ -143,5 +155,6 @@
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -5,13 +5,13 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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@ -41,7 +41,7 @@
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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@ -168,6 +168,8 @@
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#define ANOMALY_05000431 (1)
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/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
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#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* Preboot Cannot be Used to Alter the PLL_DIV Register */
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@ -204,10 +206,22 @@
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#define ANOMALY_05000467 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
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#define ANOMALY_05000483 (1)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -223,6 +237,7 @@
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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@ -259,6 +274,5 @@
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#endif
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@ -5,7 +5,7 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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@ -208,8 +208,14 @@
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#define ANOMALY_05000461 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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@ -358,6 +364,6 @@
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -5,7 +5,7 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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@ -162,8 +162,14 @@
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#define ANOMALY_05000461 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -179,6 +185,7 @@
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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@ -211,6 +218,6 @@
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -5,14 +5,14 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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* - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -132,10 +132,18 @@
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#define ANOMALY_05000443 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -185,6 +193,6 @@
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -5,7 +5,7 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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@ -28,7 +28,7 @@
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
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/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
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#define ANOMALY_05000220 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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@ -210,10 +210,16 @@
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#define ANOMALY_05000473 (1)
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/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
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#define ANOMALY_05000474 (1)
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/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
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#define ANOMALY_05000483 (1)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -229,6 +235,7 @@
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000475 (0)
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#endif
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@ -5,7 +5,7 @@
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2009 Analog Devices Inc.
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* Copyright 2004-2010 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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@ -152,8 +152,8 @@
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#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
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/* NMI Event at Boot Time Results in Unpredictable State */
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#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
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/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
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#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
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/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
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#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
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/* Incorrect Pulse-Width of UART Start Bit */
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#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
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/* Scratchpad Memory Bank Reads May Return Incorrect Data */
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@ -290,10 +290,14 @@
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#define ANOMALY_05000461 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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#define ANOMALY_05000473 (1)
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/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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#define ANOMALY_05000491 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000119 (0)
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@ -319,5 +323,6 @@
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000485 (0)
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#endif
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