ethernet: codespell comment spelling fixes
To test a checkpatch spelling patch, I ran codespell against
drivers/net/ethernet/.
$ git ls-files drivers/net/ethernet/ | \
while read file ; do \
codespell -w $file; \
done
I removed a false positive in e1000_hw.h
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Joe Perches
David S. Miller
parent
cbe21d92e4
commit
dbedd44e98
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@ -757,7 +757,7 @@ static void emac_shutdown(struct net_device *dev)
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/* Disable all interrupt */
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writel(0, db->membase + EMAC_INT_CTL_REG);
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/* clear interupt status */
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/* clear interrupt status */
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reg_val = readl(db->membase + EMAC_INT_STA_REG);
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writel(reg_val, db->membase + EMAC_INT_STA_REG);
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@ -723,13 +723,13 @@ static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
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* the last correctly noting the error.
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*/
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if(status & ERR_BIT) {
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/* reseting flags */
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/* resetting flags */
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lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
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goto err_next_pkt;
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}
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/* check for STP and ENP */
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if(!((status & STP_BIT) && (status & ENP_BIT))){
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/* reseting flags */
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/* resetting flags */
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lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
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goto err_next_pkt;
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}
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@ -614,7 +614,7 @@ typedef enum {
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/* Assume contoller gets data 10 times the maximum processing time */
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#define REPEAT_CNT 10
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/* amd8111e decriptor flag definitions */
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/* amd8111e descriptor flag definitions */
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typedef enum {
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OWN_BIT = (1 << 15),
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@ -620,7 +620,7 @@ struct xgbe_hw_features {
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unsigned int mgk; /* PMT magic packet */
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unsigned int mmc; /* RMON module */
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unsigned int aoe; /* ARP Offload */
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unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
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unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
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unsigned int eee; /* Energy Efficient Ethernet */
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unsigned int tx_coe; /* Tx Checksum Offload */
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unsigned int rx_coe; /* Rx Checksum Offload */
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@ -720,7 +720,7 @@ static irqreturn_t mace_interrupt(int irq, void *dev_id)
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mace_reset(dev);
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/*
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* XXX mace likes to hang the machine after a xmtfs error.
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* This is hard to reproduce, reseting *may* help
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* This is hard to reproduce, resetting *may* help
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*/
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}
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cp = mp->tx_cmds + NCMDS_TX * i;
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@ -575,7 +575,7 @@ static irqreturn_t mace_interrupt(int irq, void *dev_id)
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mace_reset(dev);
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/*
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* XXX mace likes to hang the machine after a xmtfs error.
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* This is hard to reproduce, reseting *may* help
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* This is hard to reproduce, resetting *may* help
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*/
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}
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/* dma should have finished */
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@ -307,7 +307,7 @@ void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel)
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/*
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* atl1c_read_phy_core
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* core funtion to read register in PHY via MDIO control regsiter.
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* core function to read register in PHY via MDIO control regsiter.
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* ext: extension register (see IEEE 802.3)
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* dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
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* reg: reg to read
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@ -356,7 +356,7 @@ int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
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/*
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* atl1c_write_phy_core
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* core funtion to write to register in PHY via MDIO control regsiter.
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* core function to write to register in PHY via MDIO control register.
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* ext: extension register (see IEEE 802.3)
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* dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
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* reg: reg to write
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@ -752,7 +752,7 @@ static void atl1c_patch_assign(struct atl1c_hw *hw)
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if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
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hw->revision_id == L2CB_V21) {
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/* config acess mode */
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/* config access mode */
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pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
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REG_PCIE_DEV_MISC_CTRL);
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pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
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@ -278,7 +278,7 @@ static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
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}
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/* congestion managment port init api description
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/* congestion management port init api description
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* the api works as follows:
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* the driver should pass the cmng_init_input struct, the port_init function
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* will prepare the required internal ram structure which will be passed back
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@ -563,7 +563,7 @@ static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
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* Will return the NIG ETS registers to init values.Except
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* credit_upper_bound.
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* That isn't used in this configuration (No WFQ is enabled) and will be
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* configured acording to spec
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* configured according to spec
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*.
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******************************************************************************/
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static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
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@ -680,7 +680,7 @@ static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
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* Will return the PBF ETS registers to init values.Except
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* credit_upper_bound.
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* That isn't used in this configuration (No WFQ is enabled) and will be
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* configured acording to spec
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* configured according to spec
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*.
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******************************************************************************/
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static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
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@ -738,7 +738,7 @@ static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
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}
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/******************************************************************************
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* Description:
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* E3B0 disable will return basicly the values to init values.
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* E3B0 disable will return basically the values to init values.
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*.
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******************************************************************************/
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static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
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@ -761,7 +761,7 @@ static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
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/******************************************************************************
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* Description:
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* Disable will return basicly the values to init values.
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* Disable will return basically the values to init values.
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*
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******************************************************************************/
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int bnx2x_ets_disabled(struct link_params *params,
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@ -2938,7 +2938,7 @@ static int bnx2x_eee_initial_config(struct link_params *params,
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{
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vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
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/* Propogate params' bits --> vars (for migration exposure) */
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/* Propagate params' bits --> vars (for migration exposure) */
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if (params->eee_mode & EEE_MODE_ENABLE_LPI)
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vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
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else
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@ -13308,7 +13308,7 @@ static void bnx2x_check_over_curr(struct link_params *params,
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vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
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}
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/* Returns 0 if no change occured since last check; 1 otherwise. */
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/* Returns 0 if no change occurred since last check; 1 otherwise. */
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static u8 bnx2x_analyze_link_error(struct link_params *params,
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struct link_vars *vars, u32 status,
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u32 phy_flag, u32 link_flag, u8 notify)
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@ -29,7 +29,7 @@
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#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
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/* [RW 1] Initiate the ATC array - reset all the valid bits */
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#define ATC_REG_ATC_INIT_ARRAY 0x1100b8
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/* [R 1] ATC initalization done */
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/* [R 1] ATC initialization done */
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#define ATC_REG_ATC_INIT_DONE 0x1100bc
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/* [RC 6] Interrupt register #0 read clear */
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#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
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@ -1620,7 +1620,7 @@ void bnx2x_memset_stats(struct bnx2x *bp)
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if (bp->port.pmf && bp->port.port_stx)
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bnx2x_port_stats_base_init(bp);
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/* mark the end of statistics initializiation */
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/* mark the end of statistics initialization */
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bp->stats_init = false;
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}
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@ -800,7 +800,7 @@ int bnx2x_vfpf_config_rss(struct bnx2x *bp,
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req->rss_key_size = T_ETH_RSS_KEY;
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req->rss_result_mask = params->rss_result_mask;
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/* flags handled individually for backward/forward compatability */
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/* flags handled individually for backward/forward compatibility */
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if (params->rss_flags & (1 << BNX2X_RSS_MODE_DISABLED))
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req->rss_flags |= VFPF_RSS_MODE_DISABLED;
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if (params->rss_flags & (1 << BNX2X_RSS_MODE_REGULAR))
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@ -1869,7 +1869,7 @@ static void bnx2x_vf_mbx_update_rss(struct bnx2x *bp, struct bnx2x_virtf *vf,
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rss.rss_obj = &vf->rss_conf_obj;
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rss.rss_result_mask = rss_tlv->rss_result_mask;
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/* flags handled individually for backward/forward compatability */
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/* flags handled individually for backward/forward compatibility */
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rss.rss_flags = 0;
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rss.ramrod_flags = 0;
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@ -135,7 +135,7 @@ struct bfa_cee_lldp_str {
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u8 value[BFA_CEE_LLDP_MAX_STRING_LEN];
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};
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/* LLDP paramters */
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/* LLDP parameters */
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struct bfa_cee_lldp_cfg {
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struct bfa_cee_lldp_str chassis_id;
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struct bfa_cee_lldp_str port_id;
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@ -1340,7 +1340,7 @@ bfa_ioc_fwver_md5_check(struct bfi_ioc_image_hdr *fwhdr_1,
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return true;
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}
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/* Returns TRUE if major minor and maintainence are same.
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/* Returns TRUE if major minor and maintenance are same.
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* If patch version are same, check for MD5 Checksum to be same.
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*/
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static bool
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@ -699,7 +699,7 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb)
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/*
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* Ignore mode and program for the max clock (which is FC16)
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* Firmware/NFC will do the PLL init appropiately
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* Firmware/NFC will do the PLL init appropriately
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
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@ -159,8 +159,8 @@ enum bfi_asic_gen {
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};
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enum bfi_asic_mode {
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BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */
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BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */
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BFI_ASIC_MODE_FC = 1, /* FC up to 8G speed */
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BFI_ASIC_MODE_FC16 = 2, /* FC up to 16G speed */
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BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */
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BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */
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};
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@ -363,7 +363,7 @@ struct bna_txq_wi_vector {
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/* TxQ Entry Structure
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*
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* BEWARE: Load values into this structure with correct endianess.
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* BEWARE: Load values into this structure with correct endianness.
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*/
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struct bna_txq_entry {
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union {
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@ -47,9 +47,9 @@
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#define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
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#define XGMAC_PMT 0x00000704 /* PMT Control and Status */
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#define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
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#define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
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#define XGMAC_MMC_INTR_RX 0x00000804 /* Receive Interrupt */
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#define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
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#define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
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#define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Receive Interrupt Mask */
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#define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
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/* Hardware TX Statistics Counters */
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@ -153,7 +153,7 @@
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#define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
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#define XGMAC_FLOW_CTRL_PT_SHIFT 16
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#define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
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#define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
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#define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshold */
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#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
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#define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
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#define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
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@ -254,18 +254,18 @@
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/* XGMAC Operation Mode Register */
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#define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
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#define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
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#define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
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#define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshold Ctrl */
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#define XGMAC_OMR_TTC_MASK 0x00030000
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#define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
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#define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
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#define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
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#define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
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#define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshold */
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#define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshold MASK */
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#define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshold */
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#define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshold MASK */
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#define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
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#define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
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#define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
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#define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
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#define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */
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#define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
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#define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshold Ctrl */
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#define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshold Ctrl MASK */
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/* XGMAC HW Features Register */
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#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
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@ -840,7 +840,7 @@ static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
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* Read the specified number of 32-bit words from the serial flash.
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* If @byte_oriented is set the read data is stored as a byte array
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* (i.e., big-endian), otherwise as 32-bit words in the platform's
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* natural endianess.
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* natural endianness.
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*/
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static int t3_read_flash(struct adapter *adapter, unsigned int addr,
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unsigned int nwords, u32 *data, int byte_oriented)
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@ -5366,7 +5366,7 @@ static int adap_init0(struct adapter *adap)
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adap->tids.stid_base = val[1];
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adap->tids.nstids = val[2] - val[1] + 1;
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/*
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* Setup server filter region. Divide the availble filter
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* Setup server filter region. Divide the available filter
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* region into two parts. Regular filters get 1/3rd and server
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* filters get 2/3rd part. This is only enabled if workarond
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* path is enabled.
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@ -867,7 +867,7 @@ static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
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* Read the specified number of 32-bit words from the serial flash.
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* If @byte_oriented is set the read data is stored as a byte array
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* (i.e., big-endian), otherwise as 32-bit words in the platform's
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* natural endianess.
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* natural endianness.
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*/
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int t4_read_flash(struct adapter *adapter, unsigned int addr,
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unsigned int nwords, u32 *data, int byte_oriented)
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@ -3558,7 +3558,7 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
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* For the single-MTU buffers in unpacked mode we need to include
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* space for the SGE Control Packet Shift, 14 byte Ethernet header,
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* possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
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* Padding boundry. All of these are accommodated in the Factory
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* Padding boundary. All of these are accommodated in the Factory
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* Default Firmware Configuration File but we need to adjust it for
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* this host's cache line size.
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*/
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@ -4529,7 +4529,7 @@ int t4_init_tp_params(struct adapter *adap)
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PROTOCOL_F);
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/* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
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* represents the presense of an Outer VLAN instead of a VNIC ID.
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* represents the presence of an Outer VLAN instead of a VNIC ID.
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*/
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if ((adap->params.tp.ingress_config & VNIC_F) == 0)
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adap->params.tp.vnic_shift = -1;
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@ -36,7 +36,7 @@
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#define _T4FW_INTERFACE_H_
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enum fw_retval {
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FW_SUCCESS = 0, /* completed sucessfully */
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FW_SUCCESS = 0, /* completed successfully */
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FW_EPERM = 1, /* operation not permitted */
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FW_ENOENT = 2, /* no such file or directory */
|
||||
FW_EIO = 5, /* input/output error; hw bad */
|
||||
|
|
|
|||
|
|
@ -875,7 +875,7 @@ static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
|
|||
* Write Header (incorporated as part of the cpl_tx_pkt_lso and
|
||||
* cpl_tx_pkt structures), followed by either a TX Packet Write CPL
|
||||
* message or, if we're doing a Large Send Offload, an LSO CPL message
|
||||
* with an embeded TX Packet Write CPL message.
|
||||
* with an embedded TX Packet Write CPL message.
|
||||
*/
|
||||
flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
|
||||
if (skb_shinfo(skb)->gso_size)
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@ int t4vf_port_init(struct adapter *adapter, int pidx)
|
|||
* @adapter: the adapter
|
||||
*
|
||||
* Issues a reset command to FW. For a Physical Function this would
|
||||
* result in the Firmware reseting all of its state. For a Virtual
|
||||
* result in the Firmware resetting all of its state. For a Virtual
|
||||
* Function this just resets the state associated with the VF.
|
||||
*/
|
||||
int t4vf_fw_reset(struct adapter *adapter)
|
||||
|
|
|
|||
|
|
@ -1578,7 +1578,7 @@ out1:
|
|||
|
||||
#ifndef CONFIG_CS89x0_PLATFORM
|
||||
/*
|
||||
* This function converts the I/O port addres used by the cs89x0_probe() and
|
||||
* This function converts the I/O port address used by the cs89x0_probe() and
|
||||
* init_module() functions to the I/O memory address used by the
|
||||
* cs89x0_probe1() function.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -653,7 +653,7 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
|
|||
if ( !(db->media_mode & DMFE_AUTO) )
|
||||
db->op_mode = db->media_mode; /* Force Mode */
|
||||
|
||||
/* Initialize Transmit/Receive decriptor and CR3/4 */
|
||||
/* Initialize Transmit/Receive descriptor and CR3/4 */
|
||||
dmfe_descriptor_init(dev);
|
||||
|
||||
/* Init CR6 to program DM910x operation */
|
||||
|
|
|
|||
|
|
@ -564,7 +564,7 @@ static void uli526x_init(struct net_device *dev)
|
|||
if ( !(db->media_mode & ULI526X_AUTO) )
|
||||
db->op_mode = db->media_mode; /* Force Mode */
|
||||
|
||||
/* Initialize Transmit/Receive decriptor and CR3/4 */
|
||||
/* Initialize Transmit/Receive descriptor and CR3/4 */
|
||||
uli526x_descriptor_init(dev, ioaddr);
|
||||
|
||||
/* Init CR6 to program M526X operation */
|
||||
|
|
|
|||
|
|
@ -3021,7 +3021,7 @@ int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
|
|||
|
||||
mac_count = resp->true_mac_count + resp->pseudo_mac_count;
|
||||
/* Mac list returned could contain one or more active mac_ids
|
||||
* or one or more true or pseudo permanant mac addresses.
|
||||
* or one or more true or pseudo permanent mac addresses.
|
||||
* If an active mac_id is present, return first active mac_id
|
||||
* found.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
|
|||
*/
|
||||
writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
|
||||
|
||||
/* It is recommended to doulbe check the TMODE field in the
|
||||
/* It is recommended to double check the TMODE field in the
|
||||
* TCSR register to be cleared before the first compare counter
|
||||
* is written into TCCR register. Just add a double check.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -414,7 +414,7 @@ enum cb_status {
|
|||
|
||||
/**
|
||||
* cb_command - Command Block flags
|
||||
* @cb_tx_nc: 0: controler does CRC (normal), 1: CRC from skb memory
|
||||
* @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
|
||||
*/
|
||||
enum cb_command {
|
||||
cb_nop = 0x0000,
|
||||
|
|
|
|||
|
|
@ -1116,7 +1116,7 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (e1000_read_mac_addr(hw))
|
||||
e_err(probe, "EEPROM Read Error\n");
|
||||
}
|
||||
/* don't block initalization here due to bad MAC address */
|
||||
/* don't block initialization here due to bad MAC address */
|
||||
memcpy(netdev->dev_addr, hw->mac_addr, netdev->addr_len);
|
||||
|
||||
if (!is_valid_ether_addr(netdev->dev_addr))
|
||||
|
|
|
|||
|
|
@ -2009,7 +2009,7 @@ static int i40evf_check_reset_complete(struct i40e_hw *hw)
|
|||
*
|
||||
* This task completes the work that was begun in probe. Due to the nature
|
||||
* of VF-PF communications, we may need to wait tens of milliseconds to get
|
||||
* reponses back from the PF. Rather than busy-wait in probe and bog down the
|
||||
* responses back from the PF. Rather than busy-wait in probe and bog down the
|
||||
* whole system, we'll do it in a task so we can sleep.
|
||||
* This task only runs during driver init. Once we've established
|
||||
* communications with the PF driver and set up our netdev, the watchdog
|
||||
|
|
@ -2400,7 +2400,7 @@ static int i40evf_suspend(struct pci_dev *pdev, pm_message_t state)
|
|||
}
|
||||
|
||||
/**
|
||||
* i40evf_resume - Power managment resume routine
|
||||
* i40evf_resume - Power management resume routine
|
||||
* @pdev: PCI device information struct
|
||||
*
|
||||
* Called when the system (VM) is resumed from sleep/suspend.
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
*
|
||||
* Neither the 82576 nor the 82580 offer registers wide enough to hold
|
||||
* nanoseconds time values for very long. For the 82580, SYSTIM always
|
||||
* counts nanoseconds, but the upper 24 bits are not availible. The
|
||||
* counts nanoseconds, but the upper 24 bits are not available. The
|
||||
* frequency is adjusted by changing the 32 bit fractional nanoseconds
|
||||
* register, TIMINCA.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -2609,7 +2609,7 @@ static irqreturn_t ixgbe_msix_other(int irq, void *data)
|
|||
eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
|
||||
|
||||
/* The lower 16bits of the EICR register are for the queue interrupts
|
||||
* which should be masked here in order to not accidently clear them if
|
||||
* which should be masked here in order to not accidentally clear them if
|
||||
* the bits are high when ixgbe_msix_other is called. There is a race
|
||||
* condition otherwise which results in possible performance loss
|
||||
* especially if the ixgbe_msix_other interrupt is triggering
|
||||
|
|
|
|||
|
|
@ -488,7 +488,7 @@ static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
|
|||
* @work: pointer to the work struct
|
||||
*
|
||||
* This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
|
||||
* timestamp has been taken for the current skb. It is necesary, because the
|
||||
* timestamp has been taken for the current skb. It is necessary, because the
|
||||
* descriptor's "done" bit does not correlate with the timestamp event.
|
||||
*/
|
||||
static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ void ixgbe_enable_sriov(struct ixgbe_adapter *adapter)
|
|||
* The 82599 supports up to 64 VFs per physical function
|
||||
* but this implementation limits allocation to 63 so that
|
||||
* basic networking resources are still available to the
|
||||
* physical function. If the user requests greater thn
|
||||
* physical function. If the user requests greater than
|
||||
* 63 VFs then it is an error - reset to default of zero.
|
||||
*/
|
||||
adapter->num_vfs = min_t(unsigned int, adapter->num_vfs, IXGBE_MAX_VFS_DRV_LIMIT);
|
||||
|
|
|
|||
|
|
@ -1690,7 +1690,7 @@ enum {
|
|||
#define IXGBE_MACC_FS 0x00040000
|
||||
#define IXGBE_MAC_RX2TX_LPBK 0x00000002
|
||||
|
||||
/* Veto Bit definiton */
|
||||
/* Veto Bit definition */
|
||||
#define IXGBE_MMNGC_MNG_VETO 0x00000001
|
||||
|
||||
/* LINKS Bit Masks */
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ static s32 ixgbevf_init_hw_vf(struct ixgbe_hw *hw)
|
|||
* ixgbevf_reset_hw_vf - Performs hardware reset
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Resets the hardware by reseting the transmit and receive units, masks and
|
||||
* Resets the hardware by resetting the transmit and receive units, masks and
|
||||
* clears all interrupts.
|
||||
**/
|
||||
static s32 ixgbevf_reset_hw_vf(struct ixgbe_hw *hw)
|
||||
|
|
|
|||
|
|
@ -1423,7 +1423,7 @@ static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
|
|||
{
|
||||
struct mvpp2_prs_entry pe;
|
||||
|
||||
/* Promiscous mode - Accept unknown packets */
|
||||
/* Promiscuous mode - Accept unknown packets */
|
||||
|
||||
if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
|
||||
/* Entry exist - update port only */
|
||||
|
|
@ -3402,7 +3402,7 @@ static void mvpp2_bm_bufs_free(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool
|
|||
for (i = 0; i < bm_pool->buf_num; i++) {
|
||||
u32 vaddr;
|
||||
|
||||
/* Get buffer virtual adress (indirect access) */
|
||||
/* Get buffer virtual address (indirect access) */
|
||||
mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
|
||||
vaddr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);
|
||||
if (!vaddr)
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ enum mlx4_res_tracker_free_type {
|
|||
|
||||
/*
|
||||
*Virtual HCR structures.
|
||||
* mlx4_vhcr is the sw representation, in machine endianess
|
||||
* mlx4_vhcr is the sw representation, in machine endianness
|
||||
*
|
||||
* mlx4_vhcr_cmd is the formalized structure, the one that is passed
|
||||
* to FW to go through communication channel.
|
||||
|
|
|
|||
|
|
@ -3027,7 +3027,7 @@ int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
|
|||
|
||||
/* Call the SW implementation of write_mtt:
|
||||
* - Prepare a dummy mtt struct
|
||||
* - Translate inbox contents to simple addresses in host endianess */
|
||||
* - Translate inbox contents to simple addresses in host endianness */
|
||||
mtt.offset = 0; /* TBD this is broken but I don't handle it since
|
||||
we don't really use it */
|
||||
mtt.order = 0;
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ static void moxart_mac_setup_desc_ring(struct net_device *ndev)
|
|||
|
||||
priv->rx_head = 0;
|
||||
|
||||
/* reset the MAC controler TX/RX desciptor base address */
|
||||
/* reset the MAC controller TX/RX desciptor base address */
|
||||
writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
|
||||
writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1343,7 +1343,7 @@ static int init_nic(struct s2io_nic *nic)
|
|||
TX_PA_CFG_IGNORE_L2_ERR;
|
||||
writeq(val64, &bar0->tx_pa_cfg);
|
||||
|
||||
/* Rx DMA intialization. */
|
||||
/* Rx DMA initialization. */
|
||||
val64 = 0;
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@ static void pch_gbe_get_pauseparam(struct net_device *netdev,
|
|||
}
|
||||
|
||||
/**
|
||||
* pch_gbe_set_pauseparam - Set pause paramters
|
||||
* pch_gbe_set_pauseparam - Set pause parameters
|
||||
* @netdev: Network interface device structure
|
||||
* @pause: Pause parameters structure
|
||||
* Returns:
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@ V. Recent Changes
|
|||
incorrectly defined and corrected (as per Michel Mueller).
|
||||
|
||||
02/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
|
||||
were available before reseting the tbusy and tx_full flags
|
||||
were available before resetting the tbusy and tx_full flags
|
||||
(as per Michel Mueller).
|
||||
|
||||
03/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
|
||||
|
|
|
|||
|
|
@ -205,7 +205,7 @@ struct qlcnic_add_rings_mbx_out {
|
|||
* @phys_addr_{low|high}: DMA address of the transmit buffer
|
||||
* @cnsmr_index_{low|high}: host consumer index
|
||||
* @size: legth of transmit buffer ring
|
||||
* @intr_id: interrput id
|
||||
* @intr_id: interrupt id
|
||||
* @src: src of interrupt
|
||||
*/
|
||||
struct qlcnic_tx_mbx {
|
||||
|
|
|
|||
|
|
@ -269,7 +269,7 @@ static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
|
|||
}
|
||||
|
||||
QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
|
||||
/* Clear gracefull reset bit */
|
||||
/* Clear graceful reset bit */
|
||||
val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
|
||||
val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
|
||||
QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
|
||||
|
|
@ -889,7 +889,7 @@ static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
|
|||
* @adapter: adapter structure
|
||||
*
|
||||
* Device will remain in this state until:
|
||||
* Reset request ACK's are recieved from all the functions
|
||||
* Reset request ACK's are received from all the functions
|
||||
* Wait time exceeds max time limit
|
||||
*
|
||||
* Returns: Error code or Success(0)
|
||||
|
|
|
|||
|
|
@ -571,7 +571,7 @@ qcaspi_spi_thread(void *data)
|
|||
}
|
||||
|
||||
/* can only handle other interrupts
|
||||
* if sync has occured
|
||||
* if sync has occurred
|
||||
*/
|
||||
if (qca->sync == QCASPI_SYNC_READY) {
|
||||
if (intr_cause & SPI_INT_PKT_AVLBL)
|
||||
|
|
|
|||
|
|
@ -422,11 +422,11 @@ static int init_tx_ring(struct device *dev, u8 queue_no,
|
|||
/* assign queue number */
|
||||
tx_ring->queue_no = queue_no;
|
||||
|
||||
/* initalise counters */
|
||||
/* initialise counters */
|
||||
tx_ring->dirty_tx = 0;
|
||||
tx_ring->cur_tx = 0;
|
||||
|
||||
/* initalise TX queue lock */
|
||||
/* initialise TX queue lock */
|
||||
spin_lock_init(&tx_ring->tx_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -515,7 +515,7 @@ static int init_rx_ring(struct net_device *dev, u8 queue_no,
|
|||
goto err_free_rx_buffers;
|
||||
}
|
||||
|
||||
/* initalise counters */
|
||||
/* initialise counters */
|
||||
rx_ring->cur_rx = 0;
|
||||
rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
|
||||
priv->dma_buf_sz = bfsize;
|
||||
|
|
@ -837,7 +837,7 @@ static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
|
|||
/* free the skbuffs of the ring */
|
||||
tx_free_ring_skbufs(tx_ring);
|
||||
|
||||
/* initalise counters */
|
||||
/* initialise counters */
|
||||
tx_ring->cur_tx = 0;
|
||||
tx_ring->dirty_tx = 0;
|
||||
|
||||
|
|
@ -1176,7 +1176,7 @@ static int sxgbe_open(struct net_device *dev)
|
|||
if (priv->phydev)
|
||||
phy_start(priv->phydev);
|
||||
|
||||
/* initalise TX coalesce parameters */
|
||||
/* initialise TX coalesce parameters */
|
||||
sxgbe_tx_init_coalesce(priv);
|
||||
|
||||
if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
|
||||
|
|
@ -1721,7 +1721,7 @@ static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
|
|||
* Description:
|
||||
* This function is a driver entry point whenever ifconfig command gets
|
||||
* executed to see device statistics. Statistics are number of
|
||||
* bytes sent or received, errors occured etc.
|
||||
* bytes sent or received, errors occurred etc.
|
||||
* Return value:
|
||||
* This function returns various statistical information of device.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -3215,7 +3215,7 @@ static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev,
|
|||
return status;
|
||||
}
|
||||
|
||||
/* Fake a successfull reset, which will be performed later in efx_io_resume. */
|
||||
/* Fake a successful reset, which will be performed later in efx_io_resume. */
|
||||
static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev)
|
||||
{
|
||||
struct efx_nic *efx = pci_get_drvdata(pdev);
|
||||
|
|
|
|||
|
|
@ -645,7 +645,7 @@ static bool efx_check_tx_flush_complete(struct efx_nic *efx)
|
|||
}
|
||||
|
||||
/* Flush all the transmit queues, and continue flushing receive queues until
|
||||
* they're all flushed. Wait for the DRAIN events to be recieved so that there
|
||||
* they're all flushed. Wait for the DRAIN events to be received so that there
|
||||
* are no more RX and TX events left on any channel. */
|
||||
static int efx_farch_do_flush(struct efx_nic *efx)
|
||||
{
|
||||
|
|
@ -1108,7 +1108,7 @@ efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
|
|||
}
|
||||
|
||||
/* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
|
||||
* was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
|
||||
* was successful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
|
||||
* the RX queue back to the mask of RX queues in need of flushing.
|
||||
*/
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -6497,7 +6497,7 @@
|
|||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
|
||||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
|
||||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
|
||||
/* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
|
||||
/* Raw buffer table entries, laid out as BUFTBL_ENTRY. */
|
||||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
|
||||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
|
||||
#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
|
||||
|
|
|
|||
|
|
@ -1067,7 +1067,7 @@ void efx_siena_sriov_probe(struct efx_nic *efx)
|
|||
}
|
||||
|
||||
/* Copy the list of individual addresses into the vfdi_status.peers
|
||||
* array and auxillary pages, protected by %local_lock. Drop that lock
|
||||
* array and auxiliary pages, protected by %local_lock. Drop that lock
|
||||
* and then broadcast the address list to every VF.
|
||||
*/
|
||||
static void efx_siena_sriov_peer_work(struct work_struct *data)
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ struct vfdi_endpoint {
|
|||
* @VFDI_OP_INIT_TXQ: Initialize SRAM entries and initialize a TXQ.
|
||||
* @VFDI_OP_FINI_ALL_QUEUES: Flush all queues, finalize all queues, then
|
||||
* finalize the SRAM entries.
|
||||
* @VFDI_OP_INSERT_FILTER: Insert a MAC filter targetting the given RXQ.
|
||||
* @VFDI_OP_INSERT_FILTER: Insert a MAC filter targeting the given RXQ.
|
||||
* @VFDI_OP_REMOVE_ALL_FILTERS: Remove all filters.
|
||||
* @VFDI_OP_SET_STATUS_PAGE: Set the DMA page(s) used for status updates
|
||||
* from PF and write the initial status.
|
||||
|
|
@ -148,7 +148,7 @@ enum vfdi_op {
|
|||
* @u.init_txq.flags: Checksum offload flags.
|
||||
* @u.init_txq.addr: Array of length %u.init_txq.buf_count containing DMA
|
||||
* address of each page backing the transmit queue.
|
||||
* @u.mac_filter.rxq: Insert MAC filter at VF local address/VLAN targetting
|
||||
* @u.mac_filter.rxq: Insert MAC filter at VF local address/VLAN targeting
|
||||
* all traffic at this receive queue.
|
||||
* @u.mac_filter.flags: MAC filter flags.
|
||||
* @u.set_status_page.dma_addr: Base address for the &struct vfdi_status.
|
||||
|
|
|
|||
|
|
@ -609,7 +609,7 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
|
|||
* where, freq_div_ratio = clk_ptp_ref_i/50MHz
|
||||
* hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
|
||||
* NOTE: clk_ptp_ref_i should be >= 50MHz to
|
||||
* achive 20ns accuracy.
|
||||
* achieve 20ns accuracy.
|
||||
*
|
||||
* 2^x * y == (y << x), hence
|
||||
* 2^32 * 50000000 ==> (50000000 << 32)
|
||||
|
|
|
|||
|
|
@ -2175,7 +2175,7 @@ static int gem_do_start(struct net_device *dev)
|
|||
}
|
||||
|
||||
/* Mark us as attached again if we come from resume(), this has
|
||||
* no effect if we weren't detatched and needs to be done now.
|
||||
* no effect if we weren't detached and needs to be done now.
|
||||
*/
|
||||
netif_device_attach(dev);
|
||||
|
||||
|
|
@ -2794,7 +2794,7 @@ static void gem_remove_one(struct pci_dev *pdev)
|
|||
|
||||
unregister_netdev(dev);
|
||||
|
||||
/* Ensure reset task is truely gone */
|
||||
/* Ensure reset task is truly gone */
|
||||
cancel_work_sync(&gp->reset_task);
|
||||
|
||||
/* Free resources */
|
||||
|
|
|
|||
|
|
@ -726,7 +726,7 @@ static void cpsw_rx_handler(void *token, int len, int status)
|
|||
if (ndev_status && (status >= 0)) {
|
||||
/* The packet received is for the interface which
|
||||
* is already down and the other interface is up
|
||||
* and running, intead of freeing which results
|
||||
* and running, instead of freeing which results
|
||||
* in reducing of the number of rx descriptor in
|
||||
* DMA engine, requeue skb back to cpdma.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1065,7 +1065,7 @@ refill:
|
|||
|
||||
/*
|
||||
* this call can fail, but for now, just leave this
|
||||
* decriptor without skb
|
||||
* descriptor without skb
|
||||
*/
|
||||
gelic_descr_prepare_rx(card, descr);
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ MODULE_LICENSE("GPL");
|
|||
|
||||
#define W5100_S0_REGS 0x0400
|
||||
#define W5100_S0_MR 0x0400 /* S0 Mode Register */
|
||||
#define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscous) */
|
||||
#define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscuous) */
|
||||
#define S0_MR_MACRAW_MF 0x44 /* MAC RAW mode (filtered) */
|
||||
#define W5100_S0_CR 0x0401 /* S0 Command Register */
|
||||
#define S0_CR_OPEN 0x01 /* OPEN command */
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ MODULE_LICENSE("GPL");
|
|||
#define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
|
||||
#define W5300_S0_MR 0x0200 /* S0 Mode Register */
|
||||
#define S0_MR_CLOSED 0x0000 /* Close mode */
|
||||
#define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscous) */
|
||||
#define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscuous) */
|
||||
#define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
|
||||
#define W5300_S0_CR 0x0202 /* S0 Command Register */
|
||||
#define S0_CR_OPEN 0x0001 /* OPEN command */
|
||||
|
|
|
|||
Loading…
Reference in New Issue