C6X: add basic support for TMS320C6678 SoC
This patch adds support for the TMS320C6678 SoC on an EVMC6678LE evaluation board. The 6678 is a C66x family CPU which is very similar to the already supported C64x CPUs with the addition of floating point instructions. Signed-off-by: Ken Cox <jkc@redhat.com> Signed-off-by: Mark Salter <msalter@redhat.com> CC: Aurelien Jacquiot <a-jacquiot@ti.com> CC: linux-c6x-dev@linux-c6x.org
This commit is contained in:
Ken Cox
Mark Salter
parent
f84f1f462b
commit
dbe91a2e6e
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@ -0,0 +1,83 @@
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/*
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* arch/c6x/boot/dts/evmc6678.dts
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*
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* EVMC6678 Evaluation Platform For TMS320C6678
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*
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* Copyright (C) 2012 Texas Instruments Incorporated
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*
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* Author: Ken Cox <jkc@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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*/
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/dts-v1/;
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/include/ "tms320c6678.dtsi"
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/ {
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model = "Advantech EVMC6678";
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compatible = "advantech,evmc6678";
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chosen {
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bootargs = "root=/dev/nfs ip=dhcp rw";
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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soc {
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megamod_pic: interrupt-controller@1800000 {
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interrupts = < 12 13 14 15 >;
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};
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timer8: timer@2280000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 66 >;
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};
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timer9: timer@2290000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 68 >;
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};
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timer10: timer@22A0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 70 >;
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};
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timer11: timer@22B0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 72 >;
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};
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timer12: timer@22C0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 74 >;
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};
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timer13: timer@22D0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 76 >;
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};
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timer14: timer@22E0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 78 >;
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};
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timer15: timer@22F0000 {
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interrupt-parent = <&megamod_pic>;
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interrupts = < 80 >;
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};
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clock-controller@2310000 {
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clock-frequency = <100000000>;
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};
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};
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};
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@ -0,0 +1,146 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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model = "ti,c66x";
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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model = "ti,c66x";
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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model = "ti,c66x";
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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model = "ti,c66x";
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};
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cpu@4 {
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device_type = "cpu";
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reg = <4>;
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model = "ti,c66x";
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};
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cpu@5 {
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device_type = "cpu";
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reg = <5>;
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model = "ti,c66x";
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};
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cpu@6 {
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device_type = "cpu";
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reg = <6>;
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model = "ti,c66x";
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};
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cpu@7 {
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device_type = "cpu";
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reg = <7>;
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model = "ti,c66x";
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6678";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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compatible = "ti,c64x+core-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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timer8: timer@2280000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x2280000 0x40>;
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};
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timer9: timer@2290000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x02 >;
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reg = <0x2290000 0x40>;
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};
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timer10: timer@22A0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x04 >;
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reg = <0x22A0000 0x40>;
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};
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timer11: timer@22B0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x08 >;
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reg = <0x22B0000 0x40>;
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};
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timer12: timer@22C0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x10 >;
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reg = <0x22C0000 0x40>;
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};
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timer13: timer@22D0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x20 >;
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reg = <0x22D0000 0x40>;
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};
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timer14: timer@22E0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x40 >;
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reg = <0x22E0000 0x40>;
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};
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timer15: timer@22F0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x80 >;
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reg = <0x22F0000 0x40>;
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};
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clock-controller@2310000 {
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compatible = "ti,c6678-pll", "ti,c64x+pll";
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reg = <0x02310000 0x200>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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device-state-controller@2620000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02620000 0x1000>;
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ti,dscr-devstat = <0x20>;
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ti,dscr-silicon-rev = <0x18 28 0xf>;
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ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
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0x114 5 6 0 0>;
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};
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};
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};
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@ -0,0 +1,42 @@
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CONFIG_SOC_TMS320C6678=y
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CONFIG_EXPERIMENTAL=y
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# CONFIG_LOCALVERSION_AUTO is not set
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CONFIG_SYSVIPC=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_NAMESPACES=y
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# CONFIG_UTS_NS is not set
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# CONFIG_USER_NS is not set
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# CONFIG_PID_NS is not set
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_EXPERT=y
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# CONFIG_FUTEX is not set
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# CONFIG_SLUB_DEBUG is not set
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CONFIG_MODULES=y
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CONFIG_MODULE_FORCE_LOAD=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE=""
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# CONFIG_CMDLINE_FORCE is not set
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CONFIG_BOARD_EVM6678=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=2
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CONFIG_BLK_DEV_RAM_SIZE=17000
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CONFIG_MISC_DEVICES=y
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_USB_SUPPORT is not set
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# CONFIG_IOMMU_SUPPORT is not set
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# CONFIG_MISC_FILESYSTEMS is not set
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CONFIG_CRC16=y
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# CONFIG_ENABLE_MUST_CHECK is not set
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_DEBUG_BUGVERBOSE is not set
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@ -143,6 +143,10 @@ static void __init get_cpuinfo(void)
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p->cpu_name = "C64x+";
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p->cpu_voltage = "1.2";
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break;
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case 21:
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p->cpu_name = "C66X";
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p->cpu_voltage = "1.2";
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break;
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default:
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p->cpu_name = "unknown";
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break;
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@ -14,3 +14,7 @@ config SOC_TMS320C6472
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config SOC_TMS320C6474
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bool "TMS320C6474"
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default n
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config SOC_TMS320C6678
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bool "TMS320C6678"
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default n
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@ -335,6 +335,68 @@ static void __init c6474_setup_clocks(struct device_node *node)
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}
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#endif /* CONFIG_SOC_TMS320C6474 */
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#ifdef CONFIG_SOC_TMS320C6678
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static struct clk_lookup c6678_clks[] = {
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
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CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
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CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
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CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
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CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
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CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
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CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
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CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
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CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
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CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
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CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
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CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
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CLK(NULL, "core", &c6x_core_clk),
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CLK("", NULL, NULL)
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};
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static void __init c6678_setup_clocks(struct device_node *node)
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{
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struct pll_data *pll = &c6x_soc_pll1;
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struct clk *sysclks = pll->sysclks;
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pll->flags = PLL_HAS_MUL;
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sysclks[1].flags |= FIXED_DIV_PLL;
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sysclks[1].div = 1;
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sysclks[2].div = PLLDIV2;
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sysclks[3].flags |= FIXED_DIV_PLL;
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sysclks[3].div = 2;
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sysclks[4].flags |= FIXED_DIV_PLL;
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sysclks[4].div = 3;
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sysclks[5].div = PLLDIV5;
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sysclks[6].flags |= FIXED_DIV_PLL;
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sysclks[6].div = 64;
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sysclks[7].flags |= FIXED_DIV_PLL;
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sysclks[7].div = 6;
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sysclks[8].div = PLLDIV8;
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sysclks[9].flags |= FIXED_DIV_PLL;
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sysclks[9].div = 12;
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sysclks[10].flags |= FIXED_DIV_PLL;
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sysclks[10].div = 3;
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sysclks[11].flags |= FIXED_DIV_PLL;
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sysclks[11].div = 6;
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c6x_core_clk.parent = &sysclks[0];
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c6x_i2c_clk.parent = &sysclks[7];
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c6x_clks_init(c6678_clks);
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}
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#endif /* CONFIG_SOC_TMS320C6678 */
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static struct of_device_id c6x_clkc_match[] __initdata = {
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#ifdef CONFIG_SOC_TMS320C6455
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{ .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
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@ -347,6 +409,9 @@ static struct of_device_id c6x_clkc_match[] __initdata = {
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#endif
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#ifdef CONFIG_SOC_TMS320C6474
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{ .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
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#endif
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#ifdef CONFIG_SOC_TMS320C6678
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{ .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
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#endif
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{ .compatible = "ti,c64x+pll" },
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{}
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