PCI/AER: Define aer_stats structure for AER capable devices
Define a structure to hold the AER statistics. There are 2 groups of statistics: dev_* counters that are to be collected for all AER capable devices and rootport_* counters that are collected for all (AER capable) rootports only. Allocate and free this structure when device is added or released (thus counters survive the lifetime of the device). Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -483,9 +483,11 @@ static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
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#ifdef CONFIG_PCIEAER
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void pci_no_aer(void);
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void pci_aer_init(struct pci_dev *dev);
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void pci_aer_exit(struct pci_dev *dev);
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#else
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static inline void pci_no_aer(void) { }
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static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
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static inline void pci_aer_exit(struct pci_dev *d) { }
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#endif
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#endif /* DRIVERS_PCI_H */
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@ -32,6 +32,9 @@
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#define AER_ERROR_SOURCES_MAX 100
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#define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
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#define AER_MAX_TYPEOF_UNCOR_ERRS 26 /* as per PCI_ERR_UNCOR_STATUS*/
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struct aer_err_source {
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unsigned int status;
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unsigned int id;
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@ -56,6 +59,42 @@ struct aer_rpc {
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*/
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};
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/* AER stats for the device */
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struct aer_stats {
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/*
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* Fields for all AER capable devices. They indicate the errors
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* "as seen by this device". Note that this may mean that if an
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* end point is causing problems, the AER counters may increment
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* at its link partner (e.g. root port) because the errors will be
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* "seen" by the link partner and not the the problematic end point
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* itself (which may report all counters as 0 as it never saw any
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* problems).
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*/
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/* Counters for different type of correctable errors */
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u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
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/* Counters for different type of fatal uncorrectable errors */
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u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
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/* Counters for different type of nonfatal uncorrectable errors */
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u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
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/* Total number of ERR_COR sent by this device */
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u64 dev_total_cor_errs;
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/* Total number of ERR_FATAL sent by this device */
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u64 dev_total_fatal_errs;
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/* Total number of ERR_NONFATAL sent by this device */
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u64 dev_total_nonfatal_errs;
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/*
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* Fields for Root ports & root complex event collectors only, these
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* indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
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* messages received by the root port / event collector, INCLUDING the
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* ones that are generated internally (by the rootport itself)
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*/
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u64 rootport_total_cor_errs;
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u64 rootport_total_fatal_errs;
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u64 rootport_total_nonfatal_errs;
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};
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#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
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PCI_ERR_UNC_ECRC| \
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PCI_ERR_UNC_UNSUP| \
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@ -385,9 +424,19 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
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void pci_aer_init(struct pci_dev *dev)
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{
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dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (dev->aer_cap)
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dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
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pci_cleanup_aer_error_status_regs(dev);
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}
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void pci_aer_exit(struct pci_dev *dev)
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{
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kfree(dev->aer_stats);
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dev->aer_stats = NULL;
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}
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#define AER_AGENT_RECEIVER 0
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#define AER_AGENT_REQUESTER 1
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#define AER_AGENT_COMPLETER 2
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@ -438,7 +487,7 @@ static const char *aer_error_layer[] = {
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"Transaction Layer"
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};
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static const char *aer_correctable_error_string[] = {
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static const char *aer_correctable_error_string[AER_MAX_TYPEOF_COR_ERRS] = {
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"RxErr", /* Bit Position 0 */
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NULL,
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NULL,
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@ -457,7 +506,7 @@ static const char *aer_correctable_error_string[] = {
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"HeaderOF", /* Bit Position 15 */
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};
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static const char *aer_uncorrectable_error_string[] = {
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static const char *aer_uncorrectable_error_string[AER_MAX_TYPEOF_UNCOR_ERRS] = {
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"Undefined", /* Bit Position 0 */
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NULL,
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NULL,
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@ -2064,6 +2064,7 @@ static void pci_configure_device(struct pci_dev *dev)
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static void pci_release_capabilities(struct pci_dev *dev)
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{
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pci_aer_exit(dev);
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pci_vpd_release(dev);
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pci_iov_release(dev);
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pci_free_cap_save_buffers(dev);
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@ -299,6 +299,7 @@ struct pci_dev {
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u8 hdr_type; /* PCI header type (`multi' flag masked out) */
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#ifdef CONFIG_PCIEAER
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u16 aer_cap; /* AER capability offset */
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struct aer_stats *aer_stats; /* AER stats for this device */
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#endif
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u8 pcie_cap; /* PCIe capability offset */
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u8 msi_cap; /* MSI capability offset */
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