metag: perf: fixes for interrupting perf counters
The overflow handler needs to read modify write when re-enabling the counter so as not to change the counter value as it may have been changed to ready the next interrupt on overflow. Similarly for interrupting counters metag_pmu_enable_counter needs to leave the counter value unchanged rather than resetting it to zero. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
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@ -643,13 +643,15 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
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config = tmp >> 4;
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}
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/*
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* Enabled counters start from 0. Early cores clear the count on
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* write but newer cores don't, so we make sure that the count is
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* set to 0.
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*/
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tmp = ((config & 0xf) << 28) |
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((1 << 24) << cpu_2_hwthread_id[get_cpu()]);
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if (metag_pmu->max_period)
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/*
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* Cores supporting overflow interrupts may have had the counter
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* set to a specific value that needs preserving.
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*/
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tmp |= metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
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metag_out32(tmp, PERF_COUNT(idx));
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unlock:
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
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@ -764,10 +766,16 @@ static irqreturn_t metag_pmu_counter_overflow(int irq, void *dev)
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/*
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* Enable the counter again once core overflow processing has
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* completed.
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* completed. Note the counter value may have been modified while it was
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* inactive to set it up ready for the next interrupt.
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*/
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if (!perf_event_overflow(event, &sampledata, regs))
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if (!perf_event_overflow(event, &sampledata, regs)) {
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__global_lock2(flags);
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counter = (counter & 0xff000000) |
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(metag_in32(PERF_COUNT(idx)) & 0x00ffffff);
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metag_out32(counter, PERF_COUNT(idx));
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__global_unlock2(flags);
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}
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return IRQ_HANDLED;
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}
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