net: dsa: qca8k: extend slave-bus implementations
This patch implements accessors for the QCA8337 MDIO access through the MDIO_MASTER register, which makes it possible to access the PHYs on slave-bus through the switch. In cases where the switch ports are already mapped via external "phy-phandles", the internal mdio-bus is disabled in order to prevent a duplicated discovery and enumeration of the same PHYs. Don't use mixed external and internal mdio-bus configurations, as this is not supported by the hardware. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Christian Lamparter
David S. Miller
parent
1eec7151ae
commit
db460c54b6
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@ -481,6 +481,155 @@ qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
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qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
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}
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static u32
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qca8k_port_to_phy(int port)
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{
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/* From Andrew Lunn:
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* Port 0 has no internal phy.
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* Port 1 has an internal PHY at MDIO address 0.
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* Port 2 has an internal PHY at MDIO address 1.
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* ...
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* Port 5 has an internal PHY at MDIO address 4.
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* Port 6 has no internal PHY.
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*/
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return port - 1;
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}
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static int
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qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
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{
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u32 phy, val;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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/* callee is responsible for not passing bad ports,
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* but we still would like to make spills impossible.
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*/
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phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
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QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
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QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
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QCA8K_MDIO_MASTER_DATA(data);
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qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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}
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static int
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qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
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{
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u32 phy, val;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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/* callee is responsible for not passing bad ports,
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* but we still would like to make spills impossible.
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*/
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phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
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QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
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QCA8K_MDIO_MASTER_REG_ADDR(regnum);
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qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
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if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY))
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return -ETIMEDOUT;
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val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
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QCA8K_MDIO_MASTER_DATA_MASK);
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return val;
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}
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static int
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qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
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{
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struct qca8k_priv *priv = ds->priv;
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return qca8k_mdio_write(priv, port, regnum, data);
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}
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static int
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qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
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{
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struct qca8k_priv *priv = ds->priv;
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int ret;
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ret = qca8k_mdio_read(priv, port, regnum);
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if (ret < 0)
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return 0xffff;
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return ret;
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}
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static int
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qca8k_setup_mdio_bus(struct qca8k_priv *priv)
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{
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u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
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struct device_node *ports, *port;
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int err;
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ports = of_get_child_by_name(priv->dev->of_node, "ports");
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if (!ports)
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return -EINVAL;
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for_each_available_child_of_node(ports, port) {
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err = of_property_read_u32(port, "reg", ®);
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if (err)
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return err;
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if (!dsa_is_user_port(priv->ds, reg))
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continue;
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if (of_property_read_bool(port, "phy-handle"))
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external_mdio_mask |= BIT(reg);
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else
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internal_mdio_mask |= BIT(reg);
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}
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if (!external_mdio_mask && !internal_mdio_mask) {
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dev_err(priv->dev, "no PHYs are defined.\n");
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return -EINVAL;
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}
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/* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
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* the MDIO_MASTER register also _disconnects_ the external MDC
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* passthrough to the internal PHYs. It's not possible to use both
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* configurations at the same time!
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*
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* Because this came up during the review process:
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* If the external mdio-bus driver is capable magically disabling
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* the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
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* accessors for the time being, it would be possible to pull this
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* off.
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*/
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if (!!external_mdio_mask && !!internal_mdio_mask) {
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dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
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return -EINVAL;
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}
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if (external_mdio_mask) {
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/* Make sure to disable the internal mdio bus in cases
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* a dt-overlay and driver reload changed the configuration
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*/
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qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_EN);
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return 0;
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}
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priv->ops.phy_read = qca8k_phy_read;
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priv->ops.phy_write = qca8k_phy_write;
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return 0;
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}
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static int
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qca8k_setup(struct dsa_switch *ds)
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{
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@ -502,6 +651,10 @@ qca8k_setup(struct dsa_switch *ds)
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if (IS_ERR(priv->regmap))
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pr_warn("regmap initialization failed");
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ret = qca8k_setup_mdio_bus(priv);
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if (ret)
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return ret;
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/* Initialize CPU port pad mode (xMII type, delays...) */
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phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
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if (phy_mode < 0) {
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@ -905,7 +1058,8 @@ qca8k_sw_probe(struct mdio_device *mdiodev)
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return -ENOMEM;
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priv->ds->priv = priv;
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priv->ds->ops = &qca8k_switch_ops;
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priv->ops = qca8k_switch_ops;
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priv->ds->ops = &priv->ops;
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mutex_init(&priv->reg_mutex);
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dev_set_drvdata(&mdiodev->dev, priv);
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@ -49,6 +49,18 @@
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#define QCA8K_MIB_FLUSH BIT(24)
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#define QCA8K_MIB_CPU_KEEP BIT(20)
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#define QCA8K_MIB_BUSY BIT(17)
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#define QCA8K_MDIO_MASTER_CTRL 0x3c
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#define QCA8K_MDIO_MASTER_BUSY BIT(31)
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#define QCA8K_MDIO_MASTER_EN BIT(30)
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#define QCA8K_MDIO_MASTER_READ BIT(27)
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#define QCA8K_MDIO_MASTER_WRITE 0
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#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
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#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
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#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
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#define QCA8K_MDIO_MASTER_DATA(x) (x)
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#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
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#define QCA8K_MDIO_MASTER_MAX_PORTS 5
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#define QCA8K_MDIO_MASTER_MAX_REG 32
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#define QCA8K_GOL_MAC_ADDR0 0x60
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#define QCA8K_GOL_MAC_ADDR1 0x64
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#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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@ -169,6 +181,7 @@ struct qca8k_priv {
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struct dsa_switch *ds;
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struct mutex reg_mutex;
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struct device *dev;
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struct dsa_switch_ops ops;
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};
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struct qca8k_mib_desc {
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